{"id":12983,"date":"2019-06-26T07:00:01","date_gmt":"2019-06-26T06:00:01","guid":{"rendered":"https:\/\/www.engineernewsnetwork.com\/blog\/?p=12983"},"modified":"2019-06-25T12:29:23","modified_gmt":"2019-06-25T11:29:23","slug":"20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie","status":"publish","type":"post","link":"https:\/\/www.engineernewsnetwork.com\/blog\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\/","title":{"rendered":"20-output PCIe clock buffers for next-generation servers, data centres, storage and PCIe"},"content":{"rendered":"\n<p>Microchip announces four new 20-output differential clock buffers that exceed PCIe Gen 5 jitter standards for next-generation data centre applications. <\/p>\n\n\n\n<p>The <strong><a rel=\"noreferrer noopener\" aria-label=\"ZL40292 (opens in a new tab)\" href=\"http:\/\/www.microchip.com\/wwwproducts\/ZL4029X\" target=\"_blank\">ZL40292<\/a><\/strong> (85\u03a9 termination) and <strong><a rel=\"noreferrer noopener\" aria-label=\"ZL40292 (opens in a new tab)\" href=\"http:\/\/www.microchip.com\/wwwproducts\/ZL4029X\" target=\"_blank\">ZL40293<\/a><\/strong> (100\u03a9 termination) are specifically designed to meet the new DB2000Q specification while the <strong><a rel=\"noreferrer noopener\" aria-label=\"ZL40292 (opens in a new tab)\" href=\"http:\/\/www.microchip.com\/wwwproducts\/ZL4029X\" target=\"_blank\">ZL40294<\/a><\/strong> (85\u03a9 termination) and <strong><a href=\"http:\/\/www.microchip.com\/wwwproducts\/ZL4029X\" target=\"_blank\" rel=\"noreferrer noopener\" aria-label=\"ZL40295 (opens in a new tab)\">ZL40295<\/a><\/strong> (100\u03a9 termination) are designed to meet the DB2000QL industry standard. These new devices also meet PCIe Gen 1, 2, 3 and 4 specifications.\u00a0<\/p>\n\n\n\n<p>Each buffer is an ideal complement to chipsets where distributed clocks are required across several peripheral components, such as Central Processing Units (CPUs), Field Programmable Gate Arrays (FPGAs) and Physical layers (PHYs) in data centre servers and storage devices, along with many other PCIe applications.&nbsp;<\/p>\n\n\n\n<p>The devices\u2019 low additive jitter of approximately 20 femtoseconds (~20 fs) far exceeds the DB2000Q\/QL specification of 80 femtoseconds (80 fs). This provides designers large margins to meet tight timing budgets while achieving increasing data rates. <\/p>\n\n\n\n<p>These devices will minimise jitter when distributing clocks to up to 20 outputs, thereby maintaining the integrity and quality of the clock signal through the buffer.\u00a0<\/p>\n\n\n\n<p>The new buffers achieve low power dissipation and contribute significant savings to power budgets by using Low-Power High-Speed Current Steering Logic (LP-HCSL). Compared to standard HCSL, LP-HCSL consumes one third of the power, leading to a significant decrease in power consumption. This feature also gives customers the ability to drive longer traces on their board, improving signal routing while reducing components and board space.&nbsp;<\/p>\n\n\n\n<p>The ZL40292, for example, can eliminate up to 80 termination resistors (four per output) compared to traditional HCSL buffers.<\/p>\n\n\n\n<p>The ZL40292 and ZL40293 are available now for sampling and in volume production in 72-pin 10 x 10mm QFN packages. The ZL40294 and ZL40295 are available now for sampling in the 80-pin 6 x 6 QFN packages.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Microchip announces four new 20-output differential clock buffers that exceed PCIe Gen 5 jitter standards for next-generation data centre applications. The ZL40292 (85\u03a9 termination) and ZL40293 (100\u03a9 termination) are specifically designed to meet the new DB2000Q specification while the ZL40294 (85\u03a9 termination) and ZL40295 (100\u03a9 termination) are designed to meet the DB2000QL industry standard. These &hellip;<\/p>\n","protected":false},"author":1,"featured_media":12984,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[6599,6597,6600,169,6598],"class_list":["post-12983","post","type-post","status-publish","format-standard","has-post-thumbnail","","category-process","tag-clock-buffers","tag-db2000q-ql-standards","tag-gen-5-low-jitter-specifications","tag-microchip","tag-pcie-gen-4"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>20-output PCIe clock buffers for next-generation servers, data centres, storage and PCIe - Engineer News Network<\/title>\n<meta name=\"description\" content=\"Reduces power consumption with Low-Power High-Speed Current Steering Logic (LP-HCSL)\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.engineernewsnetwork.com\/blog\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\/\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"20-output PCIe clock buffers for next-generation servers, data centres, storage and PCIe - Engineer News Network\" \/>\n<meta property=\"og:description\" content=\"Reduces power consumption with Low-Power High-Speed Current Steering Logic (LP-HCSL)\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.engineernewsnetwork.com\/blog\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\/\" \/>\n<meta property=\"og:site_name\" content=\"Engineer News Network\" \/>\n<meta property=\"article:published_time\" content=\"2019-06-26T06:00:01+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2019\/06\/MC1469-Image-Microchip-DB2000-hi.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"2100\" \/>\n\t<meta property=\"og:image:height\" content=\"1500\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"admin\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"admin\" \/>\n\t<meta name=\"twitter:label2\" content=\"Estimated reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"1 minute\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\\\/\"},\"author\":{\"name\":\"admin\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\"},\"headline\":\"20-output PCIe clock buffers for next-generation servers, data centres, storage and PCIe\",\"datePublished\":\"2019-06-26T06:00:01+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\\\/\"},\"wordCount\":294,\"image\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2019\\\/06\\\/MC1469-Image-Microchip-DB2000-hi.jpg\",\"keywords\":[\"clock buffers\",\"DB2000Q\\\/QL standards\",\"Gen 5 low jitter specifications\",\"Microchip\",\"PCIe Gen 4\"],\"articleSection\":[\"Process\"],\"inLanguage\":\"en-GB\"},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\\\/\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\\\/\",\"name\":\"20-output PCIe clock buffers for next-generation servers, data centres, storage and PCIe - Engineer News Network\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\\\/#primaryimage\"},\"image\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2019\\\/06\\\/MC1469-Image-Microchip-DB2000-hi.jpg\",\"datePublished\":\"2019-06-26T06:00:01+00:00\",\"author\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\"},\"description\":\"Reduces power consumption with Low-Power High-Speed Current Steering Logic (LP-HCSL)\",\"breadcrumb\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\\\/#breadcrumb\"},\"inLanguage\":\"en-GB\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\\\/\"]}]},{\"@type\":\"ImageObject\",\"inLanguage\":\"en-GB\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\\\/#primaryimage\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2019\\\/06\\\/MC1469-Image-Microchip-DB2000-hi.jpg\",\"contentUrl\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2019\\\/06\\\/MC1469-Image-Microchip-DB2000-hi.jpg\",\"width\":2100,\"height\":1500,\"caption\":\"Reduces power consumption with Low-Power High-Speed Current Steering Logic (LP-HCSL)\"},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\\\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"20-output PCIe clock buffers for next-generation servers, data centres, storage and PCIe\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#website\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/\",\"name\":\"Engineer News Network\",\"description\":\"The ultimate online news and information resource for today's engineer\",\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-GB\"},{\"@type\":\"Person\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\",\"name\":\"admin\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/author\\\/admin\\\/\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"20-output PCIe clock buffers for next-generation servers, data centres, storage and PCIe - Engineer News Network","description":"Reduces power consumption with Low-Power High-Speed Current Steering Logic (LP-HCSL)","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.engineernewsnetwork.com\/blog\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\/","og_locale":"en_GB","og_type":"article","og_title":"20-output PCIe clock buffers for next-generation servers, data centres, storage and PCIe - Engineer News Network","og_description":"Reduces power consumption with Low-Power High-Speed Current Steering Logic (LP-HCSL)","og_url":"https:\/\/www.engineernewsnetwork.com\/blog\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\/","og_site_name":"Engineer News Network","article_published_time":"2019-06-26T06:00:01+00:00","og_image":[{"width":2100,"height":1500,"url":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2019\/06\/MC1469-Image-Microchip-DB2000-hi.jpg","type":"image\/jpeg"}],"author":"admin","twitter_card":"summary_large_image","twitter_misc":{"Written by":"admin","Estimated reading time":"1 minute"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\/#article","isPartOf":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\/"},"author":{"name":"admin","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1"},"headline":"20-output PCIe clock buffers for next-generation servers, data centres, storage and PCIe","datePublished":"2019-06-26T06:00:01+00:00","mainEntityOfPage":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\/"},"wordCount":294,"image":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\/#primaryimage"},"thumbnailUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2019\/06\/MC1469-Image-Microchip-DB2000-hi.jpg","keywords":["clock buffers","DB2000Q\/QL standards","Gen 5 low jitter specifications","Microchip","PCIe Gen 4"],"articleSection":["Process"],"inLanguage":"en-GB"},{"@type":"WebPage","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\/","url":"https:\/\/www.engineernewsnetwork.com\/blog\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\/","name":"20-output PCIe clock buffers for next-generation servers, data centres, storage and PCIe - Engineer News Network","isPartOf":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#website"},"primaryImageOfPage":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\/#primaryimage"},"image":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\/#primaryimage"},"thumbnailUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2019\/06\/MC1469-Image-Microchip-DB2000-hi.jpg","datePublished":"2019-06-26T06:00:01+00:00","author":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1"},"description":"Reduces power consumption with Low-Power High-Speed Current Steering Logic (LP-HCSL)","breadcrumb":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\/#breadcrumb"},"inLanguage":"en-GB","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.engineernewsnetwork.com\/blog\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\/"]}]},{"@type":"ImageObject","inLanguage":"en-GB","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\/#primaryimage","url":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2019\/06\/MC1469-Image-Microchip-DB2000-hi.jpg","contentUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2019\/06\/MC1469-Image-Microchip-DB2000-hi.jpg","width":2100,"height":1500,"caption":"Reduces power consumption with Low-Power High-Speed Current Steering Logic (LP-HCSL)"},{"@type":"BreadcrumbList","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/20-output-pcie-clock-buffers-for-next-generation-servers-data-centres-storage-and-pcie\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/www.engineernewsnetwork.com\/blog\/"},{"@type":"ListItem","position":2,"name":"20-output PCIe clock buffers for next-generation servers, data centres, storage and PCIe"}]},{"@type":"WebSite","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#website","url":"https:\/\/www.engineernewsnetwork.com\/blog\/","name":"Engineer News Network","description":"The ultimate online news and information resource for today's engineer","potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.engineernewsnetwork.com\/blog\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-GB"},{"@type":"Person","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1","name":"admin","url":"https:\/\/www.engineernewsnetwork.com\/blog\/author\/admin\/"}]}},"_links":{"self":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/12983","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/comments?post=12983"}],"version-history":[{"count":1,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/12983\/revisions"}],"predecessor-version":[{"id":12985,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/12983\/revisions\/12985"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/media\/12984"}],"wp:attachment":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/media?parent=12983"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/categories?post=12983"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/tags?post=12983"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}