{"id":13054,"date":"2019-07-02T11:00:44","date_gmt":"2019-07-02T10:00:44","guid":{"rendered":"https:\/\/www.engineernewsnetwork.com\/blog\/?p=13054"},"modified":"2019-07-01T09:43:22","modified_gmt":"2019-07-01T08:43:22","slug":"differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications","status":"publish","type":"post","link":"https:\/\/www.engineernewsnetwork.com\/blog\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\/","title":{"rendered":"Differential clock buffers meet demand for higher design margin in terabit communications"},"content":{"rendered":"\n

Diodes Incorporated announces the PI6C59xxxxx<\/a><\/strong> series of differential clock buffers. The series supports Ethernet speeds up to 400Gbit\/s and are well-suited for high-performance applications such as data centres and 5G basestations. <\/p>\n\n\n\n

The series supports Ethernet speeds up to 400Gbit\/s and are well-suited for high-performance applications such as data centres and 5G basestations. <\/p>\n\n\n\n

The demand for network speeds operating from 25Gbit\/s up to 400Gbit\/s (known as the Terabit Ethernet, or TbE) is increasing, putting designers of switches and routers under pressure to maintain signal integrity in more challenging environments. <\/p>\n\n\n\n

The PI6C59xxxxx series of differential clock buffers provides better signal margin while expanding the drive capability of all clock and data signals used in high-speed communications. It covers a wide number of speeds and technologies, as well as combinations of input and output configurations. <\/p>\n\n\n\n

The devices in the PI6C59xxxxx series have been designed to increase the fanout of clock sources and improve clock and\/or data distribution in communication applications operating between 1.5GHz and 6GHz. This covers 25G, 40G, 56G, 100G, and 400GbE, as demanded by a wide variety of applications where low jitter and fast rise\/fall times are required. <\/p>\n\n\n\n

The ultra-low additive jitter of the devices is around 10fs, to deliver improved jitter margins to maintain overall accuracy. <\/p>\n\n\n\n

All devices are available in the TQFN package outline, and provide good thermal conductivity in a small footprint. This is increasingly important for data center and basestation applications, where suppliers need increased power density, performance, bandwidth, and functionality. <\/p>\n\n\n\n

With 13 variants in the PI6C59xxxxx series, it covers all of the main signaling technologies used in high-speed networking, including CML (current mode logic), LVDS (low voltage differential signaling), LVPECL (low voltage positive emitter coupled logic) and SSTL (stub series terminated logic), as well as LVCMOS. <\/p>\n\n\n\n

Configurations include 2, 4, 12, and 16-output for fanout buffers and data\/clock buffers. The PI6C59xxxxx series is supplied in the TQFN package with pin counts from 16 to 48.<\/p>\n","protected":false},"excerpt":{"rendered":"

Diodes Incorporated announces the PI6C59xxxxx series of differential clock buffers. The series supports Ethernet speeds up to 400Gbit\/s and are well-suited for high-performance applications such as data centres and 5G basestations. The series supports Ethernet speeds up to 400Gbit\/s and are well-suited for high-performance applications such as data centres and 5G basestations.  The demand for …<\/p>\n","protected":false},"author":1,"featured_media":13056,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[104],"tags":[6633,906],"class_list":["post-13054","post","type-post","status-publish","format-standard","has-post-thumbnail","","category-electronics","tag-differential-clock-buffers","tag-diodes"],"yoast_head":"\nDifferential clock buffers meet demand for higher design margin in terabit communications - Engineer News Network<\/title>\n<meta name=\"description\" content=\"Diodes Incorporated announces the PI6C59xxxxx series of differential clock buffers. The series supports Ethernet speeds up to 400Gbit\/s and are well-suited for high-performance applications such as data centres and 5G basestations\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.engineernewsnetwork.com\/blog\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\/\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Differential clock buffers meet demand for higher design margin in terabit communications - Engineer News Network\" \/>\n<meta property=\"og:description\" content=\"Diodes Incorporated announces the PI6C59xxxxx series of differential clock buffers. The series supports Ethernet speeds up to 400Gbit\/s and are well-suited for high-performance applications such as data centres and 5G basestations\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.engineernewsnetwork.com\/blog\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\/\" \/>\n<meta property=\"og:site_name\" content=\"Engineer News Network\" \/>\n<meta property=\"article:published_time\" content=\"2019-07-02T10:00:44+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2019\/07\/DIO7166_PI6C59xxxxx.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"900\" \/>\n\t<meta property=\"og:image:height\" content=\"690\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"admin\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"admin\" \/>\n\t<meta name=\"twitter:label2\" content=\"Estimated reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"2 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\\\/\"},\"author\":{\"name\":\"admin\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\"},\"headline\":\"Differential clock buffers meet demand for higher design margin in terabit communications\",\"datePublished\":\"2019-07-02T10:00:44+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\\\/\"},\"wordCount\":349,\"image\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2019\\\/07\\\/DIO7166_PI6C59xxxxx.jpg\",\"keywords\":[\"Differential Clock Buffers\",\"Diodes\"],\"articleSection\":[\"Electronics\"],\"inLanguage\":\"en-GB\"},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\\\/\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\\\/\",\"name\":\"Differential clock buffers meet demand for higher design margin in terabit communications - Engineer News Network\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\\\/#primaryimage\"},\"image\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2019\\\/07\\\/DIO7166_PI6C59xxxxx.jpg\",\"datePublished\":\"2019-07-02T10:00:44+00:00\",\"author\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\"},\"description\":\"Diodes Incorporated announces the PI6C59xxxxx series of differential clock buffers. The series supports Ethernet speeds up to 400Gbit\\\/s and are well-suited for high-performance applications such as data centres and 5G basestations\",\"breadcrumb\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\\\/#breadcrumb\"},\"inLanguage\":\"en-GB\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\\\/\"]}]},{\"@type\":\"ImageObject\",\"inLanguage\":\"en-GB\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\\\/#primaryimage\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2019\\\/07\\\/DIO7166_PI6C59xxxxx.jpg\",\"contentUrl\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2019\\\/07\\\/DIO7166_PI6C59xxxxx.jpg\",\"width\":900,\"height\":690,\"caption\":\"The PI6C59xxxxx series of differential clock buffers provides better signal margin while expanding the drive capability of all clock and data signals used in high-speed communications\"},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\\\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Differential clock buffers meet demand for higher design margin in terabit communications\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#website\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/\",\"name\":\"Engineer News Network\",\"description\":\"The ultimate online news and information resource for today's engineer\",\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-GB\"},{\"@type\":\"Person\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\",\"name\":\"admin\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/author\\\/admin\\\/\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"Differential clock buffers meet demand for higher design margin in terabit communications - Engineer News Network","description":"Diodes Incorporated announces the PI6C59xxxxx series of differential clock buffers. The series supports Ethernet speeds up to 400Gbit\/s and are well-suited for high-performance applications such as data centres and 5G basestations","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.engineernewsnetwork.com\/blog\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\/","og_locale":"en_GB","og_type":"article","og_title":"Differential clock buffers meet demand for higher design margin in terabit communications - Engineer News Network","og_description":"Diodes Incorporated announces the PI6C59xxxxx series of differential clock buffers. The series supports Ethernet speeds up to 400Gbit\/s and are well-suited for high-performance applications such as data centres and 5G basestations","og_url":"https:\/\/www.engineernewsnetwork.com\/blog\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\/","og_site_name":"Engineer News Network","article_published_time":"2019-07-02T10:00:44+00:00","og_image":[{"width":900,"height":690,"url":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2019\/07\/DIO7166_PI6C59xxxxx.jpg","type":"image\/jpeg"}],"author":"admin","twitter_card":"summary_large_image","twitter_misc":{"Written by":"admin","Estimated reading time":"2 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\/#article","isPartOf":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\/"},"author":{"name":"admin","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1"},"headline":"Differential clock buffers meet demand for higher design margin in terabit communications","datePublished":"2019-07-02T10:00:44+00:00","mainEntityOfPage":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\/"},"wordCount":349,"image":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\/#primaryimage"},"thumbnailUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2019\/07\/DIO7166_PI6C59xxxxx.jpg","keywords":["Differential Clock Buffers","Diodes"],"articleSection":["Electronics"],"inLanguage":"en-GB"},{"@type":"WebPage","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\/","url":"https:\/\/www.engineernewsnetwork.com\/blog\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\/","name":"Differential clock buffers meet demand for higher design margin in terabit communications - Engineer News Network","isPartOf":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#website"},"primaryImageOfPage":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\/#primaryimage"},"image":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\/#primaryimage"},"thumbnailUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2019\/07\/DIO7166_PI6C59xxxxx.jpg","datePublished":"2019-07-02T10:00:44+00:00","author":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1"},"description":"Diodes Incorporated announces the PI6C59xxxxx series of differential clock buffers. The series supports Ethernet speeds up to 400Gbit\/s and are well-suited for high-performance applications such as data centres and 5G basestations","breadcrumb":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\/#breadcrumb"},"inLanguage":"en-GB","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.engineernewsnetwork.com\/blog\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\/"]}]},{"@type":"ImageObject","inLanguage":"en-GB","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\/#primaryimage","url":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2019\/07\/DIO7166_PI6C59xxxxx.jpg","contentUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2019\/07\/DIO7166_PI6C59xxxxx.jpg","width":900,"height":690,"caption":"The PI6C59xxxxx series of differential clock buffers provides better signal margin while expanding the drive capability of all clock and data signals used in high-speed communications"},{"@type":"BreadcrumbList","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/differential-clock-buffers-meet-demand-for-higher-design-margin-in-terabit-communications\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/www.engineernewsnetwork.com\/blog\/"},{"@type":"ListItem","position":2,"name":"Differential clock buffers meet demand for higher design margin in terabit communications"}]},{"@type":"WebSite","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#website","url":"https:\/\/www.engineernewsnetwork.com\/blog\/","name":"Engineer News Network","description":"The ultimate online news and information resource for today's engineer","potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.engineernewsnetwork.com\/blog\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-GB"},{"@type":"Person","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1","name":"admin","url":"https:\/\/www.engineernewsnetwork.com\/blog\/author\/admin\/"}]}},"_links":{"self":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/13054","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/comments?post=13054"}],"version-history":[{"count":1,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/13054\/revisions"}],"predecessor-version":[{"id":13057,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/13054\/revisions\/13057"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/media\/13056"}],"wp:attachment":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/media?parent=13054"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/categories?post=13054"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/tags?post=13054"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}