{"id":14995,"date":"2019-12-11T06:00:00","date_gmt":"2019-12-11T06:00:00","guid":{"rendered":"https:\/\/www.engineernewsnetwork.com\/blog\/?p=14995"},"modified":"2019-12-10T10:31:20","modified_gmt":"2019-12-10T10:31:20","slug":"openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation","status":"publish","type":"post","link":"https:\/\/www.engineernewsnetwork.com\/blog\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\/","title":{"rendered":"OpenHW Group announces CORE-V Chassis SoC project and issues industry call for participation"},"content":{"rendered":"\n<p>With the <strong><a href=\"http:\/\/openhwgroup.com\/\" target=\"_blank\" rel=\"noreferrer noopener\" aria-label=\" (opens in a new tab)\">CORE-V Chassis project<\/a><\/strong>, the recently formed OpenHW Group aims to tape out a heterogeneous multi-core processor evaluation SoC, capable of running the Linux operating system during the 2nd half of 2020.\u00a0<\/p>\n\n\n\n<p>The CORE-V Chassis will see a CV64A 64-bit core running alongside a CV32E 32-bit coprocessor core.&nbsp;<\/p>\n\n\n\n<p>Based on the proven NXP iMX platform, the resulting CORE-V Chassis evaluation SoC will also feature 3D and 2D GPUs, MIPI-DSI and CSI display and camera I\/O, hardware security blocks, PCIe connectivity, a GigE MAC, USB 2.0 interfaces, support for (LP)DDR4, and multiple SDIO interfaces, along with a wide range of further peripheral blocks.<\/p>\n\n\n\n<p>The 64-bit CV64A core in the CORE-V Chassis is based on the RV64GC RISC-V core IP, originally developed as part of the PULP Platform at the University of ETH Zurich.<\/p>\n\n\n\n<p>Optimised for performance, the CV64A core will be capable of clock frequencies of 1.5GHz and alongside the CV64A, is a highly capable CV32E coprocessor core based on the RV32IMFCXpulp RISC-V core IP, also from the University of ETH Zurich.<\/p>\n\n\n\n<p>&#8220;NXP is thrilled to be a key contributor to the CORE-V Chassis project leveraging our world class iMX platform,\u201d said Rob Oshana, Chairman of the Board at OpenHW Group and VP Software Engineering at NXP.\u00a0 \u201cWe see the CORE-V Chassis project as a natural evolution towards enabling high volume production of OpenHW Group open-source RISC-V cores.<br><\/p>\n\n\n\n<p>OpenHW Group President and CEO, Rick O\u2019Connor, stated that \u201cThe CORE-V Chassis project will help validate that serious silicon development is possible utilising the ethos of open-source hardware, IP and tools. With the tape out of a functional evaluation SoC during the 2nd half of 2020, we will demonstrate that the open hardware mindset is as capable and dependable as any of today\u2019s closed-source alternatives.\u201d \u00a0<\/p>\n\n\n\n<p>Once completed, the CORE-V Chassis is earmarked to form the basis of further multi-core evaluation SoCs.&nbsp; Supported by members of the OpenHW Group, the CORE-V Chassis announcement is an open call for industry participation in this ambitious project. &nbsp;<\/p>\n\n\n\n<p>OpenHW Group welcomes organisations that want to get involved and help shape the direction of the CORE-V Chassis initiative.&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>With the CORE-V Chassis project, the recently formed OpenHW Group aims to tape out a heterogeneous multi-core processor evaluation SoC, capable of running the Linux operating system during the 2nd half of 2020.\u00a0 The CORE-V Chassis will see a CV64A 64-bit core running alongside a CV32E 32-bit coprocessor core.&nbsp; Based on the proven NXP iMX &hellip;<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[104,199],"tags":[7578,7577],"class_list":["post-14995","post","type-post","status-publish","format-standard","","category-electronics","category-news-views-and-opinion","tag-core-v-chassis-soc-project","tag-openhw"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>OpenHW Group announces CORE-V Chassis SoC project and issues industry call for participation - Engineer News Network<\/title>\n<meta name=\"description\" content=\"CORE-V Chassis SoC to include CORE-V family of open-source RISC-V cores including a Linux capable 64-bit processor coupled with a 32-bit coprocessor\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.engineernewsnetwork.com\/blog\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\/\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"OpenHW Group announces CORE-V Chassis SoC project and issues industry call for participation - Engineer News Network\" \/>\n<meta property=\"og:description\" content=\"CORE-V Chassis SoC to include CORE-V family of open-source RISC-V cores including a Linux capable 64-bit processor coupled with a 32-bit coprocessor\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.engineernewsnetwork.com\/blog\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\/\" \/>\n<meta property=\"og:site_name\" content=\"Engineer News Network\" \/>\n<meta property=\"article:published_time\" content=\"2019-12-11T06:00:00+00:00\" \/>\n<meta name=\"author\" content=\"admin\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"admin\" \/>\n\t<meta name=\"twitter:label2\" content=\"Estimated reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"2 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\\\/\"},\"author\":{\"name\":\"admin\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\"},\"headline\":\"OpenHW Group announces CORE-V Chassis SoC project and issues industry call for participation\",\"datePublished\":\"2019-12-11T06:00:00+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\\\/\"},\"wordCount\":376,\"keywords\":[\"CORE-V Chassis SoC project\",\"OpenHW\"],\"articleSection\":[\"Electronics\",\"News, Views and Opinion\"],\"inLanguage\":\"en-GB\"},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\\\/\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\\\/\",\"name\":\"OpenHW Group announces CORE-V Chassis SoC project and issues industry call for participation - Engineer News Network\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#website\"},\"datePublished\":\"2019-12-11T06:00:00+00:00\",\"author\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\"},\"description\":\"CORE-V Chassis SoC to include CORE-V family of open-source RISC-V cores including a Linux capable 64-bit processor coupled with a 32-bit coprocessor\",\"breadcrumb\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\\\/#breadcrumb\"},\"inLanguage\":\"en-GB\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\\\/\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\\\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"OpenHW Group announces CORE-V Chassis SoC project and issues industry call for participation\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#website\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/\",\"name\":\"Engineer News Network\",\"description\":\"The ultimate online news and information resource for today's engineer\",\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-GB\"},{\"@type\":\"Person\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\",\"name\":\"admin\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/author\\\/admin\\\/\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"OpenHW Group announces CORE-V Chassis SoC project and issues industry call for participation - Engineer News Network","description":"CORE-V Chassis SoC to include CORE-V family of open-source RISC-V cores including a Linux capable 64-bit processor coupled with a 32-bit coprocessor","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.engineernewsnetwork.com\/blog\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\/","og_locale":"en_GB","og_type":"article","og_title":"OpenHW Group announces CORE-V Chassis SoC project and issues industry call for participation - Engineer News Network","og_description":"CORE-V Chassis SoC to include CORE-V family of open-source RISC-V cores including a Linux capable 64-bit processor coupled with a 32-bit coprocessor","og_url":"https:\/\/www.engineernewsnetwork.com\/blog\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\/","og_site_name":"Engineer News Network","article_published_time":"2019-12-11T06:00:00+00:00","author":"admin","twitter_card":"summary_large_image","twitter_misc":{"Written by":"admin","Estimated reading time":"2 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\/#article","isPartOf":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\/"},"author":{"name":"admin","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1"},"headline":"OpenHW Group announces CORE-V Chassis SoC project and issues industry call for participation","datePublished":"2019-12-11T06:00:00+00:00","mainEntityOfPage":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\/"},"wordCount":376,"keywords":["CORE-V Chassis SoC project","OpenHW"],"articleSection":["Electronics","News, Views and Opinion"],"inLanguage":"en-GB"},{"@type":"WebPage","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\/","url":"https:\/\/www.engineernewsnetwork.com\/blog\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\/","name":"OpenHW Group announces CORE-V Chassis SoC project and issues industry call for participation - Engineer News Network","isPartOf":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#website"},"datePublished":"2019-12-11T06:00:00+00:00","author":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1"},"description":"CORE-V Chassis SoC to include CORE-V family of open-source RISC-V cores including a Linux capable 64-bit processor coupled with a 32-bit coprocessor","breadcrumb":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\/#breadcrumb"},"inLanguage":"en-GB","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.engineernewsnetwork.com\/blog\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\/"]}]},{"@type":"BreadcrumbList","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/openhw-group-announces-core-v-chassis-soc-project-and-issues-industry-call-for-participation\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/www.engineernewsnetwork.com\/blog\/"},{"@type":"ListItem","position":2,"name":"OpenHW Group announces CORE-V Chassis SoC project and issues industry call for participation"}]},{"@type":"WebSite","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#website","url":"https:\/\/www.engineernewsnetwork.com\/blog\/","name":"Engineer News Network","description":"The ultimate online news and information resource for today's engineer","potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.engineernewsnetwork.com\/blog\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-GB"},{"@type":"Person","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1","name":"admin","url":"https:\/\/www.engineernewsnetwork.com\/blog\/author\/admin\/"}]}},"_links":{"self":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/14995","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/comments?post=14995"}],"version-history":[{"count":1,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/14995\/revisions"}],"predecessor-version":[{"id":14996,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/14995\/revisions\/14996"}],"wp:attachment":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/media?parent=14995"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/categories?post=14995"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/tags?post=14995"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}