SiFive<\/a><\/strong>\u2019s RISC-V processor cores, and now its J-Link probes deliver support for the new SiFive Insight debug\/trace solution. This includes SiFive\u2019s latest Nexus-based trace implementation, which enables ongoing monitoring and recording of processor instruction execution.<\/p>\n\n\n\nVia SEGGER’s J-Link PLUS, PRO and ULTRA debug probe options, plus the accompanying Ozone debugger and performance analysis software package, engineers are now able to take full advantage of SiFive Insight using on-chip trace functionality.\u00a0<\/p>\n\n\n\n
Among the relevant features incorporated within the SEGGER debug probes is a backtracing capability (where the full execution history can be easily accessed and stepped through backwards). <\/p>\n\n\n\n
More advanced features, like code coverage and profiling, can also be employed – based on the execution counters processed by the J-Link software.\u00a0<\/p>\n\n\n\n
The Ozone debug software package can subsequently generate detailed code coverage reports for software validation purposes.<\/p>\n\n\n\n
\u201cThe continued support from SEGGER is a great asset to the RISC-V ecosystem, and the swift adoption of SiFive Insight is of great benefit to chip designers,\u201d says Drew Barbier, Director of Product Marketing at SiFive. \u201cSEGGER has supported SiFive Core IP since 2017 and continues to be a valued partner in the expansion and adoption of RISC-V for embedded solutions. We look forward to continued cooperation as the RISC-V ecosystem continues to grow and evolve.\u201d<\/p>\n\n\n\n
\u201cSiFive continues to innovate with solid offerings for the global RISC-V community,\u201d adds Rolf Segger, founder of SEGGER. \u201cWe are proud to support its team\u2019s efforts by offering high quality development tools and ensuring that the exciting new features they are introducing can be fully leveraged using our industry-leading Ozone debugger software and J-Link debug probe products.\u201d<\/p>\n","protected":false},"excerpt":{"rendered":"
SEGGER continues to strengthen its position in relation to the RISC-V instruction set architecture.\u00a0 The company\u2019s products are already fully compatible with SiFive\u2019s RISC-V processor cores, and now its J-Link probes deliver support for the new SiFive Insight debug\/trace solution. This includes SiFive\u2019s latest Nexus-based trace implementation, which enables ongoing monitoring and recording of processor …<\/p>\n","protected":false},"author":1,"featured_media":15950,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[7953,3675,7954],"class_list":["post-15949","post","type-post","status-publish","format-standard","has-post-thumbnail","","category-process","tag-debug-trace-platform","tag-segger","tag-sifive-insight"],"yoast_head":"\n
SEGGER support for SiFive Insight debug\/trace platform - Engineer News Network<\/title>\n<meta name=\"description\" content=\"SEGGER continues to strengthen its position in relation to the RISC-V instruction set architecture\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"SEGGER support for SiFive Insight debug\/trace platform - Engineer News Network\" \/>\n<meta property=\"og:description\" content=\"SEGGER continues to strengthen its position in relation to the RISC-V instruction set architecture\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/\" \/>\n<meta property=\"og:site_name\" content=\"Engineer News Network\" \/>\n<meta property=\"article:published_time\" content=\"2020-03-30T09:00:00+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2020\/03\/SEGGER-PR81-SiFive.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"1076\" \/>\n\t<meta property=\"og:image:height\" content=\"671\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"admin\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"admin\" \/>\n\t<meta name=\"twitter:label2\" content=\"Estimated reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"1 minute\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/#article\",\"isPartOf\":{\"@id\":\"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/\"},\"author\":{\"name\":\"admin\",\"@id\":\"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1\"},\"headline\":\"SEGGER support for SiFive Insight debug\/trace platform\",\"datePublished\":\"2020-03-30T09:00:00+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/\"},\"wordCount\":303,\"image\":{\"@id\":\"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/#primaryimage\"},\"thumbnailUrl\":\"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2020\/03\/SEGGER-PR81-SiFive.jpg\",\"keywords\":[\"debug\/trace platform\",\"Segger\",\"SiFive Insight\"],\"articleSection\":[\"Process\"],\"inLanguage\":\"en-GB\"},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/\",\"url\":\"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/\",\"name\":\"SEGGER support for SiFive Insight debug\/trace platform - Engineer News Network\",\"isPartOf\":{\"@id\":\"https:\/\/www.engineernewsnetwork.com\/blog\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/#primaryimage\"},\"image\":{\"@id\":\"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/#primaryimage\"},\"thumbnailUrl\":\"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2020\/03\/SEGGER-PR81-SiFive.jpg\",\"datePublished\":\"2020-03-30T09:00:00+00:00\",\"author\":{\"@id\":\"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1\"},\"description\":\"SEGGER continues to strengthen its position in relation to the RISC-V instruction set architecture\",\"breadcrumb\":{\"@id\":\"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/#breadcrumb\"},\"inLanguage\":\"en-GB\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/\"]}]},{\"@type\":\"ImageObject\",\"inLanguage\":\"en-GB\",\"@id\":\"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/#primaryimage\",\"url\":\"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2020\/03\/SEGGER-PR81-SiFive.jpg\",\"contentUrl\":\"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2020\/03\/SEGGER-PR81-SiFive.jpg\",\"width\":1076,\"height\":671,\"caption\":\"Company's products already fully compatible with SiFive\u2019s RISC-V processor cores, and now its J-Link probes deliver support for the new SiFive Insight debug\/trace solution\"},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\/\/www.engineernewsnetwork.com\/blog\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"SEGGER support for SiFive Insight debug\/trace platform\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/www.engineernewsnetwork.com\/blog\/#website\",\"url\":\"https:\/\/www.engineernewsnetwork.com\/blog\/\",\"name\":\"Engineer News Network\",\"description\":\"The ultimate online news and information resource for today's engineer\",\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/www.engineernewsnetwork.com\/blog\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-GB\"},{\"@type\":\"Person\",\"@id\":\"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1\",\"name\":\"admin\",\"url\":\"https:\/\/www.engineernewsnetwork.com\/blog\/author\/admin\/\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"SEGGER support for SiFive Insight debug\/trace platform - Engineer News Network","description":"SEGGER continues to strengthen its position in relation to the RISC-V instruction set architecture","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/","og_locale":"en_GB","og_type":"article","og_title":"SEGGER support for SiFive Insight debug\/trace platform - Engineer News Network","og_description":"SEGGER continues to strengthen its position in relation to the RISC-V instruction set architecture","og_url":"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/","og_site_name":"Engineer News Network","article_published_time":"2020-03-30T09:00:00+00:00","og_image":[{"width":1076,"height":671,"url":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2020\/03\/SEGGER-PR81-SiFive.jpg","type":"image\/jpeg"}],"author":"admin","twitter_card":"summary_large_image","twitter_misc":{"Written by":"admin","Estimated reading time":"1 minute"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/#article","isPartOf":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/"},"author":{"name":"admin","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1"},"headline":"SEGGER support for SiFive Insight debug\/trace platform","datePublished":"2020-03-30T09:00:00+00:00","mainEntityOfPage":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/"},"wordCount":303,"image":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/#primaryimage"},"thumbnailUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2020\/03\/SEGGER-PR81-SiFive.jpg","keywords":["debug\/trace platform","Segger","SiFive Insight"],"articleSection":["Process"],"inLanguage":"en-GB"},{"@type":"WebPage","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/","url":"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/","name":"SEGGER support for SiFive Insight debug\/trace platform - Engineer News Network","isPartOf":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#website"},"primaryImageOfPage":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/#primaryimage"},"image":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/#primaryimage"},"thumbnailUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2020\/03\/SEGGER-PR81-SiFive.jpg","datePublished":"2020-03-30T09:00:00+00:00","author":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1"},"description":"SEGGER continues to strengthen its position in relation to the RISC-V instruction set architecture","breadcrumb":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/#breadcrumb"},"inLanguage":"en-GB","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/"]}]},{"@type":"ImageObject","inLanguage":"en-GB","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/#primaryimage","url":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2020\/03\/SEGGER-PR81-SiFive.jpg","contentUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2020\/03\/SEGGER-PR81-SiFive.jpg","width":1076,"height":671,"caption":"Company's products already fully compatible with SiFive\u2019s RISC-V processor cores, and now its J-Link probes deliver support for the new SiFive Insight debug\/trace solution"},{"@type":"BreadcrumbList","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/segger-support-for-sifive-insight-debug-trace-platform\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/www.engineernewsnetwork.com\/blog\/"},{"@type":"ListItem","position":2,"name":"SEGGER support for SiFive Insight debug\/trace platform"}]},{"@type":"WebSite","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#website","url":"https:\/\/www.engineernewsnetwork.com\/blog\/","name":"Engineer News Network","description":"The ultimate online news and information resource for today's engineer","potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.engineernewsnetwork.com\/blog\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-GB"},{"@type":"Person","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1","name":"admin","url":"https:\/\/www.engineernewsnetwork.com\/blog\/author\/admin\/"}]}},"_links":{"self":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/15949","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/comments?post=15949"}],"version-history":[{"count":1,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/15949\/revisions"}],"predecessor-version":[{"id":15952,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/15949\/revisions\/15952"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/media\/15950"}],"wp:attachment":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/media?parent=15949"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/categories?post=15949"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/tags?post=15949"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}