{"id":1880,"date":"2017-10-19T15:54:41","date_gmt":"2017-10-19T14:54:41","guid":{"rendered":"https:\/\/engineernewsnetwork.com\/blog\/?p=1880"},"modified":"2017-10-19T15:58:38","modified_gmt":"2017-10-19T14:58:38","slug":"microsemi-launches-mi-v-ecosystem","status":"publish","type":"post","link":"https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/","title":{"rendered":"Microsemi launches Mi-V ecosystem"},"content":{"rendered":"<span class=\"highlight highlight-blue\"><a href=\"http:\/\/www.microsemi.com\/design-support\/accelerate-ecosystem-partners\" target=\"_blank\" rel=\"noopener\">Microsemi<\/a><\/span> announces the company\u2019s new Mi-V ecosystem with industry leaders, to increase adoption of its RISC-V soft central processing unit (CPU) product family.<\/p>\n<p>The announcement comes as the company also introduces Mi-V RV32IMA and additional field programmable gate array (FPGA)-based soft CPU solutions ideally suited for designs utilising RISC-V open instruction set architectures (ISAs).<br \/>\n<script async src=\"\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js\"><\/script><br \/>\n<ins class=\"adsbygoogle\" style=\"display: block; text-align: center;\" data-ad-format=\"fluid\" data-ad-layout=\"in-article\" data-ad-client=\"ca-pub-7565662001938327\" data-ad-slot=\"7585079586\"><\/ins><br \/>\n<script>\n(adsbygoogle = window.adsbygoogle || []).push({});\n<\/script><br \/>\n\u201cAs a leader in RISC-V, we are pleased Microsemi is the first tier one vendor to build out a complete open RISC-V ecosystem, which not only supports our needs, but contributes to the entire development community,\u201d said Jim Aralis, chief technology officer and vice president of advanced development at Microsemi.<\/p>\n<p>\u201cCustomers can now select RISC-V for their new designs knowing a tier one vendor committed to the success of this technology is providing all the necessary tools to confidently use RISC-V soft CPUs in their products.\u201d<\/p>\n<p>RISC-V, an ISA which is a standard open architecture under the governance of the RISC-V Foundation, offers numerous benefits, including portability as well as enabling the open source community to test and improve cores at a faster pace than closed ISAs.<\/p>\n<p>As the RISC-V intellectual property (IP) core is not encrypted, it can be used to ensure trust and certifications not possible with closed architectures.<\/p>\n<p>Microsemi\u2019s new Mi-V ecosystem brings together a number of industry leaders involved in the development of RISC-V to leverage their capabilities and streamline RISC-V designs for customers. \u201cMicrium is pleased to join Microsemi\u2019s Mi-V ecosystem with our highly dependable uC\/OS-II real-time kernel, a full-featured embedded operating system,\u201d said Jean Labrosse, co-founder and chief architect at Micrium.<\/p>\n<p>\u201cAs RISC-V continues to grow in popularity, we look forward to working closely with Microsemi to support accelerated adoption of its RISC-V soft CPU product offerings as well as the entire ecosystem\u2019s RISC-V advancements.\u201d<\/p>\n<p>Microsemi\u2019s Mi-V ecosystem, part of <span class=\"highlight highlight-blue\"><a href=\"https:\/\/engineernewsnetwork.com\/blog\/newly-certified-devices-feature-hardened-pci-controller-cores\/\">Microsemi<\/a><\/span>\u2019s Accelerate Ecosystem, contains a number of components. Design tools include Microsemi\u2019s SoftConsole Eclipse-based integrated development environment (IDE), the firmware catalog and Libero PolarFire system-on-chip (SoC).<\/p>\n<p>Operating systems include Express Logic\u2019s ThreadX, Huawei LiteOS and Micrium \u00b5C\/OS-II.<\/p>\n<p>Boards include the RTG4 development kit, IGLOO2 RISC-V board from Future Electronics, PolarFire Evaluation Kit and more. Debug dongles from Microsemi and Olimex, first-stage bootloaders and numerous soft peripherals are also included. Example projects, drivers and firmware are all available on GitHub, the world\u2019s largest repository of open source software.<\/p>\n<p>Deployment of soft CPUs implemented with the R11C-V ISA is automatic and delivered to the user\u2019s desktop via Microsemi\u2019s IP Catalog. No end user license agreements are needed to gain access to the soft CPUs.<\/p>\n<p>Using RISC-V soft CPUs within the Mi-V ecosystem is simple, easy and free.<\/p>\n<p>\u201cExpress Logic is pleased to be a foundational part of Microsemi\u2019s Mi-V RISC-V ecosystem,\u201d said William E. Lamie, President, Express Logic. \u201cOur X-Ware Internet-of-Things (IoT) platform, including the industry-leading ThreadX RTOS with over 6.2 billion deployments, is the preferred embedded software platform for all designs requiring industrial-grade run-time solutions\u2014making us an ideal fit for this new consortium.\u201d<\/p>\n<p>Offering low power and an open architecture, Microsemi\u2019s PolarFire, RTG4, SmartFusion2 and IGLOO2 field programmable gate array (FPGA)-based RISC-V soft CPU cores are ideal for developing a wide variety of applications within the aerospace and defense, industrial and security markets. The Mi-V soft CPU cores make them particularly suitable for applications including guided munitions, IoT, secure communications and wireline bridging.<\/p>\n<p>\u201cThe open source, royalty-free RISC-V instruction set creates a new business model for CPU designers that is garnering increasing interest and support,\u201d said Linley Gwennap, principal analyst with The Linley Group, which\u00a0named the RISC-V ISA \u201cBest Technology of 2016\u201d at its annual Analysts&#8217; Choice Awards in January 2017. \u201cBy introducing the RV32IM CPU core with support from the Mi-V ecosystem, Microsemi will play an important role in boosting the adoption of RISC-V.\u201d<\/p>\n<p>Through Microsemi\u2019s early involvement in the creation of the RISC-V Foundation, the company has an established leadership role in the emerging standard and ecosystem and is working closely with the nonprofit to ensure the ISA becomes an industry standard for a wide variety of computing devices.<\/p>\n<p>Ted Speers, head of product architecture and planning for Microsemi\u2019s Programmable business unit, was appointed to the inaugural board of directors of the RISC-V Foundation in July 2016, and Ted Marena, director of SoC FPGA marketing, was recently sworn in as chair of the RISC-V Marketing Committee after serving as vice-chair since August 2016. Marena will also be the featured speaker at EE World Online\u2019s upcoming webinar titled, \u201cThe RISC-V ecosystem is ready for prime time. Get started here!\u201d on Oct. 25, 2017. Attendees can register online to join this event.<\/p>\n<p>The Mi-V Ecosystem began as part of the Microsemi Accelerate Ecosystem, a program designed to reduce time to market for end customers and time to revenue for ecosystem participants.<\/p>\n<p>Microsemi&#8217;s Accelerate Ecosystem brings together leading silicon, intellectual property (IP), systems, software and design experts to deliver solutions for end customers.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Microsemi announces the company\u2019s new Mi-V ecosystem with industry leaders, to increase adoption of its RISC-V soft central processing unit (CPU) product family. The announcement comes as the company also introduces Mi-V RV32IMA and additional field programmable gate array (FPGA)-based soft CPU solutions ideally suited for designs utilising RISC-V open instruction set architectures (ISAs). \u201cAs &hellip;<\/p>\n","protected":false},"author":1,"featured_media":1881,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[104],"tags":[625,597,626],"class_list":["post-1880","post","type-post","status-publish","format-standard","has-post-thumbnail","","category-electronics","tag-mi-v-ecosystem","tag-microsemi","tag-risc-v-program"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Microsemi launches Mi-V ecosystem - Engineer News Network<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Microsemi launches Mi-V ecosystem - Engineer News Network\" \/>\n<meta property=\"og:description\" content=\"Microsemi announces the company\u2019s new Mi-V ecosystem with industry leaders, to increase adoption of its RISC-V soft central processing unit (CPU) product family. The announcement comes as the company also introduces Mi-V RV32IMA and additional field programmable gate array (FPGA)-based soft CPU solutions ideally suited for designs utilising RISC-V open instruction set architectures (ISAs). \u201cAs &hellip;\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/\" \/>\n<meta property=\"og:site_name\" content=\"Engineer News Network\" \/>\n<meta property=\"article:published_time\" content=\"2017-10-19T14:54:41+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2017-10-19T14:58:38+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2017\/10\/RISC-V_yellow_board.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"3303\" \/>\n\t<meta property=\"og:image:height\" content=\"1925\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"admin\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"admin\" \/>\n\t<meta name=\"twitter:label2\" content=\"Estimated reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"4 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/microsemi-launches-mi-v-ecosystem\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/microsemi-launches-mi-v-ecosystem\\\/\"},\"author\":{\"name\":\"admin\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\"},\"headline\":\"Microsemi launches Mi-V ecosystem\",\"datePublished\":\"2017-10-19T14:54:41+00:00\",\"dateModified\":\"2017-10-19T14:58:38+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/microsemi-launches-mi-v-ecosystem\\\/\"},\"wordCount\":841,\"commentCount\":0,\"image\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/microsemi-launches-mi-v-ecosystem\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2017\\\/10\\\/RISC-V_yellow_board.jpg\",\"keywords\":[\"Mi-V Ecosystem\",\"Microsemi\",\"RISC-V Program\"],\"articleSection\":[\"Electronics\"],\"inLanguage\":\"en-GB\",\"potentialAction\":[{\"@type\":\"CommentAction\",\"name\":\"Comment\",\"target\":[\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/microsemi-launches-mi-v-ecosystem\\\/#respond\"]}]},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/microsemi-launches-mi-v-ecosystem\\\/\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/microsemi-launches-mi-v-ecosystem\\\/\",\"name\":\"Microsemi launches Mi-V ecosystem - Engineer News Network\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/microsemi-launches-mi-v-ecosystem\\\/#primaryimage\"},\"image\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/microsemi-launches-mi-v-ecosystem\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2017\\\/10\\\/RISC-V_yellow_board.jpg\",\"datePublished\":\"2017-10-19T14:54:41+00:00\",\"dateModified\":\"2017-10-19T14:58:38+00:00\",\"author\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\"},\"breadcrumb\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/microsemi-launches-mi-v-ecosystem\\\/#breadcrumb\"},\"inLanguage\":\"en-GB\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/microsemi-launches-mi-v-ecosystem\\\/\"]}]},{\"@type\":\"ImageObject\",\"inLanguage\":\"en-GB\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/microsemi-launches-mi-v-ecosystem\\\/#primaryimage\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2017\\\/10\\\/RISC-V_yellow_board.jpg\",\"contentUrl\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2017\\\/10\\\/RISC-V_yellow_board.jpg\",\"width\":3303,\"height\":1925},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/microsemi-launches-mi-v-ecosystem\\\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Microsemi launches Mi-V ecosystem\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#website\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/\",\"name\":\"Engineer News Network\",\"description\":\"The ultimate online news and information resource for today's engineer\",\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-GB\"},{\"@type\":\"Person\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\",\"name\":\"admin\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/author\\\/admin\\\/\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"Microsemi launches Mi-V ecosystem - Engineer News Network","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/","og_locale":"en_GB","og_type":"article","og_title":"Microsemi launches Mi-V ecosystem - Engineer News Network","og_description":"Microsemi announces the company\u2019s new Mi-V ecosystem with industry leaders, to increase adoption of its RISC-V soft central processing unit (CPU) product family. The announcement comes as the company also introduces Mi-V RV32IMA and additional field programmable gate array (FPGA)-based soft CPU solutions ideally suited for designs utilising RISC-V open instruction set architectures (ISAs). \u201cAs &hellip;","og_url":"https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/","og_site_name":"Engineer News Network","article_published_time":"2017-10-19T14:54:41+00:00","article_modified_time":"2017-10-19T14:58:38+00:00","og_image":[{"width":3303,"height":1925,"url":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2017\/10\/RISC-V_yellow_board.jpg","type":"image\/jpeg"}],"author":"admin","twitter_card":"summary_large_image","twitter_misc":{"Written by":"admin","Estimated reading time":"4 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/#article","isPartOf":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/"},"author":{"name":"admin","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1"},"headline":"Microsemi launches Mi-V ecosystem","datePublished":"2017-10-19T14:54:41+00:00","dateModified":"2017-10-19T14:58:38+00:00","mainEntityOfPage":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/"},"wordCount":841,"commentCount":0,"image":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/#primaryimage"},"thumbnailUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2017\/10\/RISC-V_yellow_board.jpg","keywords":["Mi-V Ecosystem","Microsemi","RISC-V Program"],"articleSection":["Electronics"],"inLanguage":"en-GB","potentialAction":[{"@type":"CommentAction","name":"Comment","target":["https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/#respond"]}]},{"@type":"WebPage","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/","url":"https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/","name":"Microsemi launches Mi-V ecosystem - Engineer News Network","isPartOf":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#website"},"primaryImageOfPage":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/#primaryimage"},"image":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/#primaryimage"},"thumbnailUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2017\/10\/RISC-V_yellow_board.jpg","datePublished":"2017-10-19T14:54:41+00:00","dateModified":"2017-10-19T14:58:38+00:00","author":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1"},"breadcrumb":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/#breadcrumb"},"inLanguage":"en-GB","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/"]}]},{"@type":"ImageObject","inLanguage":"en-GB","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/#primaryimage","url":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2017\/10\/RISC-V_yellow_board.jpg","contentUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2017\/10\/RISC-V_yellow_board.jpg","width":3303,"height":1925},{"@type":"BreadcrumbList","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/microsemi-launches-mi-v-ecosystem\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/www.engineernewsnetwork.com\/blog\/"},{"@type":"ListItem","position":2,"name":"Microsemi launches Mi-V ecosystem"}]},{"@type":"WebSite","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#website","url":"https:\/\/www.engineernewsnetwork.com\/blog\/","name":"Engineer News Network","description":"The ultimate online news and information resource for today's engineer","potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.engineernewsnetwork.com\/blog\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-GB"},{"@type":"Person","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1","name":"admin","url":"https:\/\/www.engineernewsnetwork.com\/blog\/author\/admin\/"}]}},"_links":{"self":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/1880","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/comments?post=1880"}],"version-history":[{"count":4,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/1880\/revisions"}],"predecessor-version":[{"id":1885,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/1880\/revisions\/1885"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/media\/1881"}],"wp:attachment":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/media?parent=1880"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/categories?post=1880"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/tags?post=1880"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}