{"id":31586,"date":"2026-03-26T09:00:00","date_gmt":"2026-03-26T09:00:00","guid":{"rendered":"https:\/\/www.engineernewsnetwork.com\/blog\/?p=31586"},"modified":"2026-03-17T09:38:25","modified_gmt":"2026-03-17T09:38:25","slug":"ultra-low-power-analogue-processing-units","status":"publish","type":"post","link":"https:\/\/www.engineernewsnetwork.com\/blog\/ultra-low-power-analogue-processing-units\/","title":{"rendered":"Ultra-low power analogue processing units"},"content":{"rendered":"\n<p>Mythic has chosen memBrain neuromorphic hardware intellectual property (IP) from <strong><a href=\"http:\/\/www.microchip.com\">Microchip Technology<\/a><\/strong>\u2019s  Silicon Storage Technology (SST) subsidiary for its next-generation edge to enterprise Analog Processing Units (APUs). <\/p>\n\n\n\n<p>Mythic will utilise SST&#8217;s SuperFlash embedded non-volatile memory (eNVM) bitcells to deliver high levels of analog compute-in-memory (aCIM) performance per watt. The partnership enables Mythic to achieve 120 TOPS\/watt inference processing for power-efficient AI acceleration at the edge and in the data center: Mythic&#8217;s APUs are targeted to be up to 100 times more energy-efficient than conventional digital Graphics Processing Units (GPUs).<\/p>\n\n\n\n<p>One hundred fifty billion units of SST SuperFlash technology that Mythic is licensing have been shipped to date. SuperFlash technology is the de facto eNVM solution for a broad spectrum of industries including industrial, automotive, consumer and computing for critical data and code storage, and is licensed by all of the top ten semiconductor foundries worldwide.<\/p>\n\n\n\n<p>The memBrain cell features:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Up to 8 data bits per bitcell (8 bpc) storage<\/li>\n\n\n\n<li>Single-digit nanoamp (nA) bitcell read current<\/li>\n\n\n\n<li>10-year data retention at operating temperature<\/li>\n\n\n\n<li>100,000 endurance cycles<\/li>\n\n\n\n<li>Full state machine control of the 8 bpc multi-state write operation<\/li>\n\n\n\n<li>Single cycle multiply-and-accumulate operations for aCIM<\/li>\n\n\n\n<li><\/li>\n<\/ul>\n\n\n\n<p>SST\u2019s memBrain technology has been developed and deployed in 40nm and 28nm foundry processes using production-ready SuperFlash memory. 22nm memBrain development is planned to extend the technology roadmap. Designed to provide reliable, high-performance and low-power non-volatile storage directly on the chip, SuperFlash memory is widely used in applications that require fast access times, high endurance and data retention without the need for external memory components.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Mythic has chosen memBrain neuromorphic hardware intellectual property (IP) from Microchip Technology\u2019s Silicon Storage Technology (SST) subsidiary for its next-generation edge to enterprise Analog Processing Units (APUs). Mythic will utilise SST&#8217;s SuperFlash embedded non-volatile memory (eNVM) bitcells to deliver high levels of analog compute-in-memory (aCIM) performance per watt. The partnership enables Mythic to achieve 120 &hellip;<\/p>\n","protected":false},"author":1,"featured_media":31587,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[104],"tags":[14578,14581,14577,14579,14580],"class_list":["post-31586","post","type-post","status-publish","format-standard","has-post-thumbnail","","category-electronics","tag-membrain","tag-microchip-technology-2","tag-mythic","tag-silicon-storage-technolog","tag-ultra-low-power-analogue-processing-units"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Ultra-low power analogue processing units - Engineer News Network<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.engineernewsnetwork.com\/blog\/ultra-low-power-analogue-processing-units\/\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Ultra-low power analogue processing units - Engineer News Network\" \/>\n<meta property=\"og:description\" content=\"Mythic has chosen memBrain neuromorphic hardware intellectual property (IP) from Microchip Technology\u2019s Silicon Storage Technology (SST) subsidiary for its next-generation edge to enterprise Analog Processing Units (APUs). Mythic will utilise SST&#8217;s SuperFlash embedded non-volatile memory (eNVM) bitcells to deliver high levels of analog compute-in-memory (aCIM) performance per watt. The partnership enables Mythic to achieve 120 &hellip;\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.engineernewsnetwork.com\/blog\/ultra-low-power-analogue-processing-units\/\" \/>\n<meta property=\"og:site_name\" content=\"Engineer News Network\" \/>\n<meta property=\"article:published_time\" content=\"2026-03-26T09:00:00+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2026\/03\/MC1731-Image-MythicAI-scaled.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"2560\" \/>\n\t<meta property=\"og:image:height\" content=\"1422\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"admin\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"admin\" \/>\n\t<meta name=\"twitter:label2\" content=\"Estimated reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"2 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/ultra-low-power-analogue-processing-units\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/ultra-low-power-analogue-processing-units\\\/\"},\"author\":{\"name\":\"admin\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\"},\"headline\":\"Ultra-low power analogue processing units\",\"datePublished\":\"2026-03-26T09:00:00+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/ultra-low-power-analogue-processing-units\\\/\"},\"wordCount\":258,\"image\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/ultra-low-power-analogue-processing-units\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2026\\\/03\\\/MC1731-Image-MythicAI-scaled.jpg\",\"keywords\":[\"memBrain\",\"Microchip Technology\u2019\",\"Mythic\",\"Silicon Storage Technolog\",\"Ultra-Low-Power Analogue Processing Units\"],\"articleSection\":[\"Electronics\"],\"inLanguage\":\"en-GB\"},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/ultra-low-power-analogue-processing-units\\\/\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/ultra-low-power-analogue-processing-units\\\/\",\"name\":\"Ultra-low power analogue processing units - Engineer News Network\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/ultra-low-power-analogue-processing-units\\\/#primaryimage\"},\"image\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/ultra-low-power-analogue-processing-units\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2026\\\/03\\\/MC1731-Image-MythicAI-scaled.jpg\",\"datePublished\":\"2026-03-26T09:00:00+00:00\",\"author\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\"},\"breadcrumb\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/ultra-low-power-analogue-processing-units\\\/#breadcrumb\"},\"inLanguage\":\"en-GB\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/ultra-low-power-analogue-processing-units\\\/\"]}]},{\"@type\":\"ImageObject\",\"inLanguage\":\"en-GB\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/ultra-low-power-analogue-processing-units\\\/#primaryimage\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2026\\\/03\\\/MC1731-Image-MythicAI-scaled.jpg\",\"contentUrl\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2026\\\/03\\\/MC1731-Image-MythicAI-scaled.jpg\",\"width\":2560,\"height\":1422,\"caption\":\"With SuperFlash memory, Mythic\u2019s APU achieves120 TOPs\\\/watt performance for low-power AI inferencing\"},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/ultra-low-power-analogue-processing-units\\\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Ultra-low power analogue processing units\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#website\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/\",\"name\":\"Engineer News Network\",\"description\":\"The ultimate online news and information resource for today's engineer\",\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-GB\"},{\"@type\":\"Person\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\",\"name\":\"admin\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/author\\\/admin\\\/\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"Ultra-low power analogue processing units - Engineer News Network","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.engineernewsnetwork.com\/blog\/ultra-low-power-analogue-processing-units\/","og_locale":"en_GB","og_type":"article","og_title":"Ultra-low power analogue processing units - Engineer News Network","og_description":"Mythic has chosen memBrain neuromorphic hardware intellectual property (IP) from Microchip Technology\u2019s Silicon Storage Technology (SST) subsidiary for its next-generation edge to enterprise Analog Processing Units (APUs). Mythic will utilise SST&#8217;s SuperFlash embedded non-volatile memory (eNVM) bitcells to deliver high levels of analog compute-in-memory (aCIM) performance per watt. The partnership enables Mythic to achieve 120 &hellip;","og_url":"https:\/\/www.engineernewsnetwork.com\/blog\/ultra-low-power-analogue-processing-units\/","og_site_name":"Engineer News Network","article_published_time":"2026-03-26T09:00:00+00:00","og_image":[{"width":2560,"height":1422,"url":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2026\/03\/MC1731-Image-MythicAI-scaled.jpg","type":"image\/jpeg"}],"author":"admin","twitter_card":"summary_large_image","twitter_misc":{"Written by":"admin","Estimated reading time":"2 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/ultra-low-power-analogue-processing-units\/#article","isPartOf":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/ultra-low-power-analogue-processing-units\/"},"author":{"name":"admin","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1"},"headline":"Ultra-low power analogue processing units","datePublished":"2026-03-26T09:00:00+00:00","mainEntityOfPage":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/ultra-low-power-analogue-processing-units\/"},"wordCount":258,"image":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/ultra-low-power-analogue-processing-units\/#primaryimage"},"thumbnailUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2026\/03\/MC1731-Image-MythicAI-scaled.jpg","keywords":["memBrain","Microchip Technology\u2019","Mythic","Silicon Storage Technolog","Ultra-Low-Power Analogue Processing Units"],"articleSection":["Electronics"],"inLanguage":"en-GB"},{"@type":"WebPage","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/ultra-low-power-analogue-processing-units\/","url":"https:\/\/www.engineernewsnetwork.com\/blog\/ultra-low-power-analogue-processing-units\/","name":"Ultra-low power analogue processing units - Engineer News Network","isPartOf":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#website"},"primaryImageOfPage":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/ultra-low-power-analogue-processing-units\/#primaryimage"},"image":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/ultra-low-power-analogue-processing-units\/#primaryimage"},"thumbnailUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2026\/03\/MC1731-Image-MythicAI-scaled.jpg","datePublished":"2026-03-26T09:00:00+00:00","author":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1"},"breadcrumb":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/ultra-low-power-analogue-processing-units\/#breadcrumb"},"inLanguage":"en-GB","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.engineernewsnetwork.com\/blog\/ultra-low-power-analogue-processing-units\/"]}]},{"@type":"ImageObject","inLanguage":"en-GB","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/ultra-low-power-analogue-processing-units\/#primaryimage","url":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2026\/03\/MC1731-Image-MythicAI-scaled.jpg","contentUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2026\/03\/MC1731-Image-MythicAI-scaled.jpg","width":2560,"height":1422,"caption":"With SuperFlash memory, Mythic\u2019s APU achieves120 TOPs\/watt performance for low-power AI inferencing"},{"@type":"BreadcrumbList","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/ultra-low-power-analogue-processing-units\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/www.engineernewsnetwork.com\/blog\/"},{"@type":"ListItem","position":2,"name":"Ultra-low power analogue processing units"}]},{"@type":"WebSite","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#website","url":"https:\/\/www.engineernewsnetwork.com\/blog\/","name":"Engineer News Network","description":"The ultimate online news and information resource for today's engineer","potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.engineernewsnetwork.com\/blog\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-GB"},{"@type":"Person","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1","name":"admin","url":"https:\/\/www.engineernewsnetwork.com\/blog\/author\/admin\/"}]}},"_links":{"self":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/31586","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/comments?post=31586"}],"version-history":[{"count":1,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/31586\/revisions"}],"predecessor-version":[{"id":31588,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/31586\/revisions\/31588"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/media\/31587"}],"wp:attachment":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/media?parent=31586"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/categories?post=31586"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/tags?post=31586"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}