{"id":32409,"date":"2026-06-03T09:15:00","date_gmt":"2026-06-03T08:15:00","guid":{"rendered":"https:\/\/www.engineernewsnetwork.com\/blog\/?p=32409"},"modified":"2026-06-03T09:07:21","modified_gmt":"2026-06-03T08:07:21","slug":"retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centres","status":"publish","type":"post","link":"https:\/\/www.engineernewsnetwork.com\/blog\/retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centres\/","title":{"rendered":"Retimers address latency and signal\u2011Integrity challenges in AI data centres"},"content":{"rendered":"\n

As AI workloads continue to scale, data centre architects are increasingly constrained by limited signal reach and rising latency, which can leave valuable memory resources underutilized across large GPU clusters. These challenges are amplified as interconnect speeds increase. At 64 GT\/s (giga transfers per second), signal integrity limitations can restrict system scale and burden server architectures. In response, Microchip Technology has released XpressConnect<\/strong><\/a> PCIe 6.0 and CXL 3.1 retimers to enable memory expansion and resource disaggregation in large-scale AI fabrics.<\/p>\n\n\n\n

The retimers are designed to extend signal reach beyond conventional PCIe Gen 5 and Gen 6 electrical limits, enabling more flexible system designs across complex baseboards, riser cards and cabled interconnects. The retimers are engineered to help address these challenges by enabling higher\u2011bandwidth connectivity while supporting the stringent thermal and power budgets required in modern AI fabrics. XpressConnect retimers achieve a pin\u2011to\u2011pin latency of less than 12ns, approximately 80% lower than PCIe 6.0 specifications. This low\u2011latency performance helps improve utilisation of AI accelerators and GPUs by reducing data stalls in high\u2011density AI clusters.<\/p>\n\n\n\n

\u201cAI data centres are increasingly constrained not by compute, but by the ability to move data efficiently across the system. As PCIe 6.0 pushes speeds to 64 GT\/s, signal reach and latency become critical design challenges,\u201d said Brian McCarson, corporate vice president and GM of Microchip\u2019s data center solutions business unit. \u201cOur XpressConnect retimers are designed to act as the high\u2011performance nerve center of the AI server, helping customers build more scalable, power\u2011efficient fabrics by reducing latency and improving connectivity across dense GPU clusters. This system\u2011level approach allows data center architects to reclaim underutilized resources and improve overall platform efficiency at scale.\u201d<\/p>\n\n\n\n

The XpressConnect retimers round out Microchip\u2019s data center portfolio and are engineered to work alongside the company\u2019s 3\u2011nm Switchtec PCIe Gen 6 switches, Adaptec SmartRAID controllers and Host Bus Adapters (HBAs) and Flashtec NVMe controllers, helping enable a pre\u2011validated, interoperable fabric. Microchip\u2019s XpressConnect PCIe Gen 6 and CXL 3.1 retimers can integrate with PCIe Gen 3, Gen 4 and Gen 5 platforms where required, which helps reduce time to market. The retimers also connect into Microchip\u2019s ChipLink diagnostic ecosystem, delivering a unified graphical user interface for real\u2011time 2D eye capture and four\u2011level pulse amplitude modulation (PAM4) telemetry. These capabilities help data center operators monitor link health more effectively and simplify troubleshooting, which can help reduce total cost of ownership.<\/p>\n","protected":false},"excerpt":{"rendered":"

As AI workloads continue to scale, data centre architects are increasingly constrained by limited signal reach and rising latency, which can leave valuable memory resources underutilized across large GPU clusters. These challenges are amplified as interconnect speeds increase. At 64 GT\/s (giga transfers per second), signal integrity limitations can restrict system scale and burden server …<\/p>\n","protected":false},"author":1,"featured_media":32410,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[104],"tags":[2732,14957],"class_list":["post-32409","post","type-post","status-publish","format-standard","has-post-thumbnail","","category-electronics","tag-microchip-technology","tag-xpressconnect"],"yoast_head":"\nRetimers address latency and signal\u2011Integrity challenges in AI data centres - Engineer News Network<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.engineernewsnetwork.com\/blog\/retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centres\/\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Retimers address latency and signal\u2011Integrity challenges in AI data centres - Engineer News Network\" \/>\n<meta property=\"og:description\" content=\"As AI workloads continue to scale, data centre architects are increasingly constrained by limited signal reach and rising latency, which can leave valuable memory resources underutilized across large GPU clusters. These challenges are amplified as interconnect speeds increase. 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