{"id":5134,"date":"2018-02-28T16:39:24","date_gmt":"2018-02-28T16:39:24","guid":{"rendered":"https:\/\/engineernewsnetwork.com\/blog\/?p=5134"},"modified":"2018-02-28T16:39:50","modified_gmt":"2018-02-28T16:39:50","slug":"imec-and-cadence-tape-out-industrys-first-3nm-test-chip","status":"publish","type":"post","link":"https:\/\/www.engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/","title":{"rendered":"Imec and Cadence tape out industry\u2019s first 3nm test chip"},"content":{"rendered":"<p>The research and innovation hub in nanoelectronics and digital technologies, <span class=\"highlight highlight-blue\"><a href=\"http:\/\/www.imec-int.com\" target=\"_blank\" rel=\"noopener\">imec<\/a><\/span>, and <span class=\"highlight highlight-blue\"><a href=\"https:\/\/www.cadence.com\/\" target=\"_blank\" rel=\"noopener\">Cadence Design Systems<\/a><\/span>, announces that its extensive, long-standing collaboration has resulted in the industry\u2019s first 3nm test chip tapeout.<\/p>\n<p>The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-orientated design rules and the Cadence Innovus Implementation System and Genus Synthesis Solution.<br \/>\n<script async src=\"\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js\"><\/script><br \/>\n<ins class=\"adsbygoogle\" style=\"display: block; text-align: center;\" data-ad-layout=\"in-article\" data-ad-format=\"fluid\" data-ad-client=\"ca-pub-7565662001938327\" data-ad-slot=\"7585079586\"><\/ins><br \/>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script><br \/>\nImec utilised a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm.<\/p>\n<p>Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.<\/p>\n<p>The Cadence Innovus Implementation System is a massively parallel physical implementation system that enables engineers to deliver high-quality designs with optimal power, performance and area (PPA) targets while accelerating time to market.<\/p>\n<p>The Cadence Genus Synthesis Solution is a next-generation, high-capacity RTL synthesis and physical synthesis engine that addresses the latest FinFET process node requirements, improving RTL designer productivity by up to 10X.<\/p>\n<p>For the project, EUV and 193i lithography rules were tested to provide the required resolution, while providing PPA comparison under two different patterning assumptions.<\/p>\n<p>\u201cAs process dimensions reduce to the 3nm node, interconnect variation becomes much more significant,\u201d said An Steegen, executive vice president for semiconductor technology and systems at imec. \u201cOur work on the test chip has enabled interconnect variation to be measured and improved and the 3nm manufacturing process to be validated. Also, the Cadence digital solutions offered everything needed for this 3nm implementation. Due to Cadence\u2019s well-integrated flow, the solutions were easy to use, which helped our engineering team stay productive when developing the 3nm rule set.\u201d<\/p>\n<p>\u201cImec\u2019s state-of-the-art infrastructure enables pre-production innovations ahead of industry demands, making them a critical partner for us in the EDA industry,\u201d said Dr. Chin-Chi Teng, corporate vice president and general manager in the Digital &amp; Signoff Group at <span class=\"highlight highlight-blue\"><a href=\"https:\/\/engineernewsnetwork.com\/blog\/providing-critical-work-in-progress-design-data\/\" target=\"_blank\" rel=\"noopener\">Cadence Design Systems<\/a><\/span>. \u201cExpanding upon the work we did with imec in 2015 on the industry\u2019s first 5nm tapeout, we are achieving new milestones together with this new 3nm tapeout, which can transform the future of mobile designs at advanced nodes.\u201d<\/p>\n","protected":false},"excerpt":{"rendered":"<p>The research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, announces that its extensive, long-standing collaboration has resulted in the industry\u2019s first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-orientated design rules and the &hellip;<\/p>\n","protected":false},"author":1,"featured_media":5135,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[104],"tags":[2802,1117,2803,2804,2801,2805],"class_list":["post-5134","post","type-post","status-publish","format-standard","has-post-thumbnail","","category-electronics","tag-3nm-test-chip-tapeout","tag-cadence-design-systems","tag-cadence-innovus-implementation-system","tag-genus-synthesis-solution","tag-imec","tag-nanoelectronics"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Imec and Cadence tape out industry\u2019s first 3nm test chip - Engineer News Network<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Imec and Cadence tape out industry\u2019s first 3nm test chip - Engineer News Network\" \/>\n<meta property=\"og:description\" content=\"The research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, announces that its extensive, long-standing collaboration has resulted in the industry\u2019s first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-orientated design rules and the &hellip;\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/\" \/>\n<meta property=\"og:site_name\" content=\"Engineer News Network\" \/>\n<meta property=\"article:published_time\" content=\"2018-02-28T16:39:24+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2018-02-28T16:39:50+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/02\/Post_place_and_route_layout_of_21nm_pitch_metal_layers.png\" \/>\n\t<meta property=\"og:image:width\" content=\"1481\" \/>\n\t<meta property=\"og:image:height\" content=\"796\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/png\" \/>\n<meta name=\"author\" content=\"admin\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"admin\" \/>\n\t<meta name=\"twitter:label2\" content=\"Estimated reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"2 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\\\/\"},\"author\":{\"name\":\"admin\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\"},\"headline\":\"Imec and Cadence tape out industry\u2019s first 3nm test chip\",\"datePublished\":\"2018-02-28T16:39:24+00:00\",\"dateModified\":\"2018-02-28T16:39:50+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\\\/\"},\"wordCount\":391,\"image\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2018\\\/02\\\/Post_place_and_route_layout_of_21nm_pitch_metal_layers.png\",\"keywords\":[\"3nm test chip tapeout\",\"Cadence Design Systems\",\"Cadence Innovus Implementation System\",\"Genus Synthesis Solution\",\"imec\",\"nanoelectronics\"],\"articleSection\":[\"Electronics\"],\"inLanguage\":\"en-GB\"},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\\\/\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\\\/\",\"name\":\"Imec and Cadence tape out industry\u2019s first 3nm test chip - Engineer News Network\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\\\/#primaryimage\"},\"image\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2018\\\/02\\\/Post_place_and_route_layout_of_21nm_pitch_metal_layers.png\",\"datePublished\":\"2018-02-28T16:39:24+00:00\",\"dateModified\":\"2018-02-28T16:39:50+00:00\",\"author\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\"},\"breadcrumb\":{\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\\\/#breadcrumb\"},\"inLanguage\":\"en-GB\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\\\/\"]}]},{\"@type\":\"ImageObject\",\"inLanguage\":\"en-GB\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\\\/#primaryimage\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2018\\\/02\\\/Post_place_and_route_layout_of_21nm_pitch_metal_layers.png\",\"contentUrl\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/wp-content\\\/uploads\\\/2018\\\/02\\\/Post_place_and_route_layout_of_21nm_pitch_metal_layers.png\",\"width\":1481,\"height\":796},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\\\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Imec and Cadence tape out industry\u2019s first 3nm test chip\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#website\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/\",\"name\":\"Engineer News Network\",\"description\":\"The ultimate online news and information resource for today's engineer\",\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-GB\"},{\"@type\":\"Person\",\"@id\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/#\\\/schema\\\/person\\\/4477342aea8e299c6a21761e513ea8e1\",\"name\":\"admin\",\"url\":\"https:\\\/\\\/www.engineernewsnetwork.com\\\/blog\\\/author\\\/admin\\\/\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"Imec and Cadence tape out industry\u2019s first 3nm test chip - Engineer News Network","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/","og_locale":"en_GB","og_type":"article","og_title":"Imec and Cadence tape out industry\u2019s first 3nm test chip - Engineer News Network","og_description":"The research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, announces that its extensive, long-standing collaboration has resulted in the industry\u2019s first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-orientated design rules and the &hellip;","og_url":"https:\/\/www.engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/","og_site_name":"Engineer News Network","article_published_time":"2018-02-28T16:39:24+00:00","article_modified_time":"2018-02-28T16:39:50+00:00","og_image":[{"width":1481,"height":796,"url":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/02\/Post_place_and_route_layout_of_21nm_pitch_metal_layers.png","type":"image\/png"}],"author":"admin","twitter_card":"summary_large_image","twitter_misc":{"Written by":"admin","Estimated reading time":"2 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/#article","isPartOf":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/"},"author":{"name":"admin","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1"},"headline":"Imec and Cadence tape out industry\u2019s first 3nm test chip","datePublished":"2018-02-28T16:39:24+00:00","dateModified":"2018-02-28T16:39:50+00:00","mainEntityOfPage":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/"},"wordCount":391,"image":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/#primaryimage"},"thumbnailUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/02\/Post_place_and_route_layout_of_21nm_pitch_metal_layers.png","keywords":["3nm test chip tapeout","Cadence Design Systems","Cadence Innovus Implementation System","Genus Synthesis Solution","imec","nanoelectronics"],"articleSection":["Electronics"],"inLanguage":"en-GB"},{"@type":"WebPage","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/","url":"https:\/\/www.engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/","name":"Imec and Cadence tape out industry\u2019s first 3nm test chip - Engineer News Network","isPartOf":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#website"},"primaryImageOfPage":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/#primaryimage"},"image":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/#primaryimage"},"thumbnailUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/02\/Post_place_and_route_layout_of_21nm_pitch_metal_layers.png","datePublished":"2018-02-28T16:39:24+00:00","dateModified":"2018-02-28T16:39:50+00:00","author":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1"},"breadcrumb":{"@id":"https:\/\/www.engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/#breadcrumb"},"inLanguage":"en-GB","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/"]}]},{"@type":"ImageObject","inLanguage":"en-GB","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/#primaryimage","url":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/02\/Post_place_and_route_layout_of_21nm_pitch_metal_layers.png","contentUrl":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/02\/Post_place_and_route_layout_of_21nm_pitch_metal_layers.png","width":1481,"height":796},{"@type":"BreadcrumbList","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/www.engineernewsnetwork.com\/blog\/"},{"@type":"ListItem","position":2,"name":"Imec and Cadence tape out industry\u2019s first 3nm test chip"}]},{"@type":"WebSite","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#website","url":"https:\/\/www.engineernewsnetwork.com\/blog\/","name":"Engineer News Network","description":"The ultimate online news and information resource for today's engineer","potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.engineernewsnetwork.com\/blog\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-GB"},{"@type":"Person","@id":"https:\/\/www.engineernewsnetwork.com\/blog\/#\/schema\/person\/4477342aea8e299c6a21761e513ea8e1","name":"admin","url":"https:\/\/www.engineernewsnetwork.com\/blog\/author\/admin\/"}]}},"_links":{"self":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/5134","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/comments?post=5134"}],"version-history":[{"count":2,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/5134\/revisions"}],"predecessor-version":[{"id":5137,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/posts\/5134\/revisions\/5137"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/media\/5135"}],"wp:attachment":[{"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/media?parent=5134"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/categories?post=5134"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.engineernewsnetwork.com\/blog\/wp-json\/wp\/v2\/tags?post=5134"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}