{"id":6685,"date":"2018-04-20T11:03:08","date_gmt":"2018-04-20T10:03:08","guid":{"rendered":"https:\/\/engineernewsnetwork.com\/blog\/?p=6685"},"modified":"2018-04-20T11:04:51","modified_gmt":"2018-04-20T10:04:51","slug":"workflow-enables-customers-to-automatically-generate-test-benches-for-hdl-verification","status":"publish","type":"post","link":"https:\/\/www.engineernewsnetwork.com\/blog\/workflow-enables-customers-to-automatically-generate-test-benches-for-hdl-verification\/","title":{"rendered":"Workflow enables customers to automatically generate test benches for HDL verification"},"content":{"rendered":"<span class=\"highlight highlight-blue\"><a href=\"http:\/\/www.microsemi.com\/products\/fpga-soc\/fpgas\" target=\"_blank\" rel=\"noopener\">Microsemi Corporation<\/a><\/span> is collaborating with <span class=\"highlight highlight-blue\"><a href=\"https:\/\/www.mathworks.com\/products\/hdl-verifier.html\" target=\"_blank\" rel=\"noopener\">MathWorks<\/a><\/span>, a developer of mathematical computing software for engineers and scientists, to launch hardware support for field programmable gate array (FPGA)-in-the-loop (FIL) verification workflow with <span class=\"highlight highlight-blue\"><a href=\"https:\/\/engineernewsnetwork.com\/blog\/microsemi-reaches-key-production-qualification-milestone-for-polarfire-fpga-family\/\" target=\"_blank\" rel=\"noopener\">Microsemi<\/a><\/span> FPGA development boards.<\/p>\n<p>The new integrated FIL workflow with HDL Coder and HDL Verifier from MathWorks enables customers to automatically generate test benches for hardware description language (HDL) verification, including VHSIC Hardware Description Language (VHDL) and Verilog, providing rapid prototyping and verification of designs.<br \/>\n<script async src=\"\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js\"><\/script><br \/>\n<ins class=\"adsbygoogle\" style=\"display: block; text-align: center;\" data-ad-layout=\"in-article\" data-ad-format=\"fluid\" data-ad-client=\"ca-pub-75656620019lko38327\" data-ad-slot=\"7585079586\"><\/ins><br \/>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script><br \/>\nThe collaboration with MathWorks enables customers to integrate\u00a0 MATLAB, a programming environment for algorithm development, data analysis, visualisation and numeric computation, and Simulink, a graphical environment for simulation and Model-Based Design, with <span class=\"highlight highlight-blue\"><a href=\"https:\/\/engineernewsnetwork.com\/blog\/microsemi-achieves-qml-class-q-qualification-for-its-rtg4-high-speed-radiation-tolerant-fpgas\/\" target=\"_blank\" rel=\"noopener\">Microsemi<\/a><\/span>\u2019s SmartFusion2 system-on-chip (SoC) FPGA and PolarFire FPGA development boards, which allows the stimulation of designs through FIL verification workflow using Microsemi\u2019s development boards.<\/p>\n<p>FIL verification workflow enables customers to analyze the results back in MATLAB and Simulink. \u201cWith the ever-increasing complexity in algorithm designs, it has become imperative for designers to quickly design and validate their algorithms on real hardware,\u201d said Shakeel Peera, vice president FPGA marketing for Microsemi. \u201cThis integrated FPGA-in-the-loop workflow of Microsemi FPGA boards with MathWorks HDL Verifier will allow system engineers and algorithm developers to quickly prototype and implement their MATLAB and Simulink designs on Microsemi FPGA development boards through our Libero SoC Design Suite.\u201d<\/p>\n<span class=\"highlight highlight-blue\"><a href=\"https:\/\/engineernewsnetwork.com\/blog\/cesium-clocks-microsemi-portfolio-compliant-with-new-itu-standards-for-enhanced-primary-reference-clock\/\" target=\"_blank\" rel=\"noopener\">Microsemi<\/a><\/span>\u2019s collaboration with MathWorks enables a unified workflow to verify designs comprehensively.<\/p>\n<p>It integrates Microsemi\u2019s Libero SoC Design Suite\u2014a comprehensive, easy to learn, easy to adopt development toolset for designing with Microsemi&#8217;s FPGAs and SoC FPGAs\u2014with MATLAB and Simulink for design verification, and provides FIL verification with Microsemi FPGA boards.<\/p>\n<p>This allows customers to catch bugs early in the design cycle, helping reduce time to market and enabling early verification.<\/p>\n<p>\u201cMATLAB and Simulink are widely used by engineers to develop algorithms targeting FPGAs,\u201d said Paul Barnard, director of marketing for the Simulink product family at MathWorks. \u201cNow that HDL Verifier supports FIL for Microsemi development kits, engineers can connect designs implemented on these FPGA boards directly to MATLAB and Simulink test benches, streamlining a crucial validation step in developing safety-critical avionics, space and other applications.\u201d<\/p>\n<p>Delivering the industry\u2019s first FIL feature for <span class=\"highlight highlight-blue\"><a href=\"https:\/\/engineernewsnetwork.com\/blog\/microsemis-polarfire-fpga\/\" target=\"_blank\" rel=\"noopener\">Microsemi<\/a><\/span> boards with MATLAB and Simulink, the collaboration provides HDL Verifier Support Package for Microsemi FPGA, a hardware support package for SmartFusion2 SoC FPGA and PolarFire FPGA development boards, and an integrated workflow from algorithms to implementation.<\/p>\n<figure id=\"attachment_6688\" aria-describedby=\"caption-attachment-6688\" style=\"width: 618px\" class=\"wp-caption alignnone\"><a href=\"https:\/\/engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/04\/CT-127_Diagrams_5-01.png\"><img loading=\"lazy\" decoding=\"async\" class=\"size-large wp-image-6688\" src=\"https:\/\/engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/04\/CT-127_Diagrams_5-01-1024x677.png\" alt=\"Workflow enables customers to automatically generate test benches for HDL verification\" width=\"618\" height=\"409\" srcset=\"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/04\/CT-127_Diagrams_5-01-1024x677.png 1024w, https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/04\/CT-127_Diagrams_5-01-300x198.png 300w, https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/04\/CT-127_Diagrams_5-01-768x507.png 768w, https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/04\/CT-127_Diagrams_5-01-310x205.png 310w, https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/04\/CT-127_Diagrams_5-01-800x529.png 800w\" sizes=\"auto, (max-width: 618px) 100vw, 618px\" \/><\/a><figcaption id=\"caption-attachment-6688\" class=\"wp-caption-text\">Microsemi Collaborates with MathWorks to Deliver First Integrated FPGA-in-the-Loop Workflow for PolarFire and SmartFusion2 FPGA Development Boards<\/figcaption><\/figure>\n<p>Leveraging HDL Verifer, enabled by Microsemi\u2019s Accelerate Ecosystem, makes Microsemi\u2019s FPGAs ideal for a wide variety of applications within the aerospace and defense, security, industrial and medical markets, including motor control and imaging, digital signal processing, communication systems, machine vision and imaging systems, control systems, military communications, and payload and radio processing.<\/p>\n<p>The usage of FPGA verification significantly reduces timelines and development costs and has experienced considerable adoption in defense, automotive and industrial markets, leading to a booming $68 million for FPGA verification since September 2017 (as of March 2018), growing at a compound annual growth rate (CAGR) of nearly 8% through 2025 according to IndustryARC.<\/p>\n<p>The market research firm also notes FPGA verification has an untapped potential market (total addressable market, or TAM) of $425 million with a tapped service addressable market (SAM) of $141 million.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Microsemi Corporation is collaborating with MathWorks, a developer of mathematical computing software for engineers and scientists, to launch hardware support for field programmable gate array (FPGA)-in-the-loop (FIL) verification workflow with Microsemi FPGA development boards. The new integrated FIL workflow with HDL Coder and HDL Verifier from MathWorks enables customers to automatically generate test benches for &hellip;<\/p>\n","protected":false},"author":1,"featured_media":6688,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[104],"tags":[3721,3720,597,3722],"class_list":["post-6685","post","type-post","status-publish","format-standard","has-post-thumbnail","","category-electronics","tag-fpga-in-the-loop-workflow-for-polarfire","tag-mathworks","tag-microsemi","tag-smartfusion2-fpga"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Workflow enables customers to automatically generate test benches for HDL verification - Engineer News Network<\/title>\n<meta name=\"description\" content=\"Microsemi Collaborates with MathWorks to Deliver First Integrated FPGA-in-the-Loop Workflow for PolarFire and SmartFusion2 FPGA Development Boards\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.engineernewsnetwork.com\/blog\/workflow-enables-customers-to-automatically-generate-test-benches-for-hdl-verification\/\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Workflow enables customers to automatically generate test benches for HDL verification - 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