{"id":6993,"date":"2018-05-02T10:00:06","date_gmt":"2018-05-02T09:00:06","guid":{"rendered":"https:\/\/engineernewsnetwork.com\/blog\/?p=6993"},"modified":"2018-05-01T18:01:32","modified_gmt":"2018-05-01T17:01:32","slug":"test-chip-fabricated-in-tsmc-7nm-process-achieves-4400mt-sec-data-rate","status":"publish","type":"post","link":"https:\/\/www.engineernewsnetwork.com\/blog\/test-chip-fabricated-in-tsmc-7nm-process-achieves-4400mt-sec-data-rate\/","title":{"rendered":"Test chip fabricated in TSMC 7nm process achieves 4400MT\/sec data rate"},"content":{"rendered":"<span class=\"highlight highlight-blue\"><a href=\"http:\/\/www.cadence.com\/go\/ddr5iptestchip\" target=\"_blank\" rel=\"noopener\">Cadence Design Systems<\/a><\/span> has prototyped its first IP interface in silicon for a preliminary version of the DDR5 standard being developed in JEDEC.<\/p>\n<p>The <span class=\"highlight highlight-blue\"><a href=\"https:\/\/engineernewsnetwork.com\/blog\/cadence-expands-virtuoso-platform\/\" target=\"_blank\" rel=\"noopener\">Cadence<\/a><\/span> test chip was fabricated in TSMC\u2019s 7nm process and achieves a 4400 megatransfers per second (MT\/sec) data rate, which is 37.5% faster than the fastest commercial DDR4 memory at 3200MT\/sec.<br \/>\n<script async src=\"\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js\"><\/script><br \/>\n<ins class=\"adsbygoogle\" style=\"display: block; text-align: center;\" data-ad-layout=\"in-article\" data-ad-format=\"fluid\" data-ad-client=\"ca-pub-7565662001938327\" data-ad-slot=\"7585079586\"><\/ins><br \/>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script><br \/>\nWith this key milestone, SoC providers developing high-speed memory subsystems for high-end server, storage and enterprise applications can start developing their DDR5 memory subsystems now with silicon-tested PHY and controller IP from <span class=\"highlight highlight-blue\"><a href=\"https:\/\/engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/\" target=\"_blank\" rel=\"noopener\">Cadence<\/a><\/span>.<\/p>\n<p>\u201cTSMC recognises the importance of next-generation DRAM for our enterprise and data center customers,\u201d said Suk Lee, senior director of the Design Infrastructure Marketing Division at TSMC. \u201cWe\u2019re pleased Cadence has proven interoperability with prototype DDR5 memory devices in our industry-leading 7nm process.<\/p>\n<p>\u201cThis demonstrates a path to higher bandwidth and density for future server and storage devices manufactured at TSMC.\u201d<\/p>\n<p>\u201cAs part of Cadence\u2019s DDR PHY validation and interoperability program, Micron has provided Cadence with engineering prototypes of the first memory for a preliminary version of the DDR5 standard,\u201d said Ryan Baxter, director of Data Center segment, Compute and Networking Business Unit, at Micron. \u201cWe are enthusiastic that Cadence\u2019s DDR5 IP test chip is able to interoperate consistently with our DDR5 prototype memory devices at the 4400MT\/sec speed.\u201d<\/p>\n<p>\u201cCadence has taken a huge leap forward in enabling servers, storage and enterprise equipment with next-generation high-speed memory. Systems that use DDR5 will be able to achieve higher bandwidth than DDR4 while also using less power per bit transferred, enabling these systems to do more computing on larger data sets than what\u2019s possible with DDR4,\u201d said Babu Mandava, senior vice president and general manager, IP Group at Cadence. \u201cCadence next-generation DDR IP is ready for implementation now, and we look forward to enabling DDR5 SoC designs.\u201d<\/p>\n<span class=\"highlight highlight-blue\"><\/span><a href=\"https:\/\/engineernewsnetwork.com\/blog\/cadence-appoints-anirudh-devgan-as-president\/\" target=\"_blank\" rel=\"noopener\">Cadence[<\/a>\/highlight] is ready to engage with customers immediately to start SoC designs integrating DDR5 memory interfaces.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Cadence Design Systems has prototyped its first IP interface in silicon for a preliminary version of the DDR5 standard being developed in JEDEC. The Cadence test chip was fabricated in TSMC\u2019s 7nm process and achieves a 4400 megatransfers per second (MT\/sec) data rate, which is 37.5% faster than the fastest commercial DDR4 memory at 3200MT\/sec. &hellip;<\/p>\n","protected":false},"author":1,"featured_media":6994,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[104],"tags":[2135,3951,3950,3952],"class_list":["post-6993","post","type-post","status-publish","format-standard","has-post-thumbnail","","category-electronics","tag-cadence","tag-ddr5","tag-ip-interface","tag-jedec"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Test chip fabricated in TSMC 7nm process achieves 4400MT\/sec data rate - Engineer News Network<\/title>\n<meta name=\"description\" content=\"Cadence Design Systems has prototyped its first IP interface in silicon for a preliminary version of the DDR5 standard being developed in JEDEC\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.engineernewsnetwork.com\/blog\/test-chip-fabricated-in-tsmc-7nm-process-achieves-4400mt-sec-data-rate\/\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Test chip fabricated in TSMC 7nm process achieves 4400MT\/sec data rate - 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