{"id":7071,"date":"2018-05-07T10:45:46","date_gmt":"2018-05-07T09:45:46","guid":{"rendered":"https:\/\/engineernewsnetwork.com\/blog\/?p=7071"},"modified":"2018-05-04T13:52:02","modified_gmt":"2018-05-04T12:52:02","slug":"cadence-shortens-automotive-verification-closure-with-new-verification-ip-for-ufs-3-0-coaxpress-and-hyperram","status":"publish","type":"post","link":"https:\/\/www.engineernewsnetwork.com\/blog\/cadence-shortens-automotive-verification-closure-with-new-verification-ip-for-ufs-3-0-coaxpress-and-hyperram\/","title":{"rendered":"Cadence shortens Automotive Verification Closure with new Verification IP for UFS 3.0, CoaxPress and HyperRAM"},"content":{"rendered":"<span class=\"highlight highlight-blue\"><a href=\"http:\/\/www.cadence.com\" target=\"_blank\" rel=\"noopener\">Cadence Design Systems<\/a><\/span> announces three new Verification IP (VIP) offerings: the industry\u2019s first CoaXPress VIP offering for high-speed imaging, the industry\u2019s first HyperRAM high-speed memory VIP offering, and a VIP offering for the new JEDEC Universal Flash Storage (UFS) 3.0 specification.<\/p>\n<p>All three enable early adopters of these standards to begin designing with the new specifications immediately, ensuring compliance with the standard and achieving the fastest path to IP and system-on-chip (SoC) verification closure.<br \/>\n<script async src=\"\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js\"><\/script><br \/>\n<ins class=\"adsbygoogle\" style=\"display: block; text-align: center;\" data-ad-layout=\"in-article\" data-ad-format=\"fluid\" data-ad-client=\"ca-pub-7565662001938327\" data-ad-slot=\"7585079586\"><\/ins><br \/>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script><br \/>\n\u201cDesigners of SoCs for automotive applications face unique challenges of sustainability and reliability together with growing real-time processing needs that drive interfaces and memory standards innovation\u201d said Michal Siwinski, vice president of product engineering and management, System and Verification Group at <span class=\"highlight highlight-blue\"><a href=\"https:\/\/engineernewsnetwork.com\/blog\/cadence-expands-virtuoso-platform\/\" target=\"_blank\" rel=\"noopener\">Cadence Design Systems<\/a><\/span>. \u201cThese three new VIP offerings add to the total Cadence Verification Suite to help engineers easily achieve compliance with the latest standards for rapid high-quality design of innovative new automotive electronics.\u201d<\/p>\n<p><strong>VIP for UFS 3.0<\/strong><\/p>\n<p>The UFS 3.0 specification doubles the throughput bandwidth from 1333MB\/s in UFS 2.1 to 2666MB\/s in UFS3.0 to address the growing bandwidth, low power and responsiveness requirements of advanced automotive and mobile designs.<\/p>\n<p>The UFS 3.0 Memory Model provides a full-stack solution, including support for MIPI\u00ae Unified Protocol (UniProSM) 1.8 and MIPI M-PHYSM 4.1, with comprehensive coverage model and test suite.<\/p>\n<p>This VIP offering also utilises Cadence TripleCheck technology for fast testing of all requirements for the specification.<\/p>\n<p>\u201cWith the continuous evolution of memory specifications and the growing complexity of the protocols, early users of new standards need access to memory models that ease adoption,\u201d said G.J. Perdaems, Senior Director of Managed NAND Solutions at Micron. \u201cOur team is already utilising the Cadence UFS Memory Model successfully, and it\u2019s encouraging to see Cadence continue its commitment to develop first-to-market solutions for the latest protocols.<\/p>\n<p>\u201cWith the <span class=\"highlight highlight-blue\"><a href=\"https:\/\/engineernewsnetwork.com\/blog\/imec-and-cadence-tape-out-industrys-first-3nm-test-chip\/\" target=\"_blank\" rel=\"noopener\">Cadence<\/a><\/span> Memory Model for UFS 3.0, our engineers can confidently verify our designs with ease so they can keep their focus on designing managed memory solutions and delivering products to market faster.\u201d<\/p>\n<p><strong>VIP for CoaXPress<\/strong><\/p>\n<p>The CoaXPress interface standard provides high-speed serial communication over coaxial cable.<\/p>\n<p>It is ideal for automated acquisition and analysis of video and images, which is becoming more important as engineers develop autonomous driving applications.<\/p>\n<p>It also can be used in other industrial and machine vision applications requiring transfer speeds up to 6.25Gbit\/s. It utilises Cadence TripleCheck technology, which provides a verification plan with measurable objectives linked to the specification features and a comprehensive test suite with thousands of ready-to-run tests to ensure support for the specification.<\/p>\n<p><strong>VIP for HyperRAM<\/strong><\/p>\n<p>HyperRAM is a high-performance 333MB\/sec read performance memory based on the HyperBus interface. It is for applications that focus on a small footprint, including automotive, industrial and consumer applications.<\/p>\n<p>These VIP offerings join the extensive Cadence VIP library, which provides a comprehensive\u00a0 portfolio for automotive applications including LPDDR 4\/5, Ethernet TSN, MIPI CSI-2SM, DSI-2SM and I3CSM,\u00a0 DisplayPort, CAN and eMMC.<\/p>\n<p>These VIP offerings are part of the <span class=\"highlight highlight-blue\"><a href=\"https:\/\/engineernewsnetwork.com\/blog\/cadence-appoints-anirudh-devgan-as-president\/\" target=\"_blank\" rel=\"noopener\">Cadence<\/a><\/span> Verification Suite and are optimised for Xcelium Parallel Logic Simulation, along with supported third-party simulators.<\/p>\n<p>They support the company\u2019s System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.<\/p>\n<p>The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Cadence Design Systems announces three new Verification IP (VIP) offerings: the industry\u2019s first CoaXPress VIP offering for high-speed imaging, the industry\u2019s first HyperRAM high-speed memory VIP offering, and a VIP offering for the new JEDEC Universal Flash Storage (UFS) 3.0 specification. All three enable early adopters of these standards to begin designing with the new &hellip;<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[104],"tags":[4007,1117,4008,4009],"class_list":["post-7071","post","type-post","status-publish","format-standard","","category-electronics","tag-automotive-verification-closure","tag-cadence-design-systems","tag-verification-ip","tag-vip"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Cadence shortens Automotive Verification Closure with new Verification IP for UFS 3.0, CoaxPress and HyperRAM - Engineer News Network<\/title>\n<meta name=\"description\" content=\"Three Verification IP offerings enable designers to quickly achieve compliance with the latest protocols\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.engineernewsnetwork.com\/blog\/cadence-shortens-automotive-verification-closure-with-new-verification-ip-for-ufs-3-0-coaxpress-and-hyperram\/\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Cadence shortens Automotive Verification Closure with new Verification IP for UFS 3.0, CoaxPress and HyperRAM - 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