{"id":8234,"date":"2018-06-27T09:00:39","date_gmt":"2018-06-27T08:00:39","guid":{"rendered":"https:\/\/engineernewsnetwork.com\/blog\/?p=8234"},"modified":"2018-06-26T10:57:54","modified_gmt":"2018-06-26T09:57:54","slug":"jitter-performance","status":"publish","type":"post","link":"https:\/\/www.engineernewsnetwork.com\/blog\/jitter-performance\/","title":{"rendered":"Clocks boost frequency flexibility and jitter performance"},"content":{"rendered":"<span class=\"highlight highlight-blue\"><a href=\"https:\/\/engineernewsnetwork.com\/blog\/silicon-labs-tackles-high-speed-transceiver-clocking-with-high-performance-oscillators\/\" target=\"_blank\" rel=\"noopener\">Silicon Labs<\/a><\/span> has expanded its timing portfolio to meet the high-performance clocking requirements of 56G PAM-4 SerDes and emerging 112G serial applications.<\/p>\n<p>With this portfolio expansion, Silicon Labs is the only timing supplier to offer a comprehensive selection of clock generators, jitter attenuating clocks, voltage-controlled crystal oscillators (VCXOs) and XOs for 100\/200\/400\/600G designs that satisfy sub-100 fs reference clock jitter requirements with margin.<\/p>\n<p>Leading manufacturers of switch SoCs, PHYs, FPGAs and ASICs, including Broadcom, Inphi, Intel, MACOM, Marvell, MediaTek and Xilinx, are migrating to 56G PAM-4 SerDes technology to support higher bandwidth 100G+ Ethernet and optical networking designs.<br \/>\n<script async src=\"\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js\"><\/script><br \/>\n<ins class=\"adsbygoogle\" style=\"display: block; text-align: center;\" data-ad-layout=\"in-article\" data-ad-format=\"fluid\" data-ad-client=\"ca-pub-7565662001938327\" data-ad-slot=\"7585079586\"><\/ins><br \/>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script><br \/>\nTo meet the stringent requirements of 56G SerDes reference clocks, hardware developers often require clocks with sub-100fs (typical) RMS phase jitter specifications.<\/p>\n<p>These designs typically use a mix of other frequencies for CPU and system clocks.<\/p>\n<figure id=\"attachment_8236\" aria-describedby=\"caption-attachment-8236\" style=\"width: 618px\" class=\"wp-caption alignnone\"><a href=\"https:\/\/engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/06\/press-1200x627-clean-e1530006749481.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"size-large wp-image-8236\" src=\"https:\/\/engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/06\/press-1200x627-clean-e1530006749481-1024x375.jpg\" alt=\"Clocks boost frequency flexibility and jitter performance\" width=\"618\" height=\"226\" srcset=\"https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/06\/press-1200x627-clean-e1530006749481-1024x375.jpg 1024w, https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/06\/press-1200x627-clean-e1530006749481-300x110.jpg 300w, https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/06\/press-1200x627-clean-e1530006749481-768x282.jpg 768w, https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/06\/press-1200x627-clean-e1530006749481-800x293.jpg 800w, https:\/\/www.engineernewsnetwork.com\/blog\/wp-content\/uploads\/2018\/06\/press-1200x627-clean-e1530006749481.jpg 1170w\" sizes=\"auto, (max-width: 618px) 100vw, 618px\" \/><\/a><figcaption id=\"caption-attachment-8236\" class=\"wp-caption-text\">Silicon Labs introduces industry\u2019s broadest portfolio for 56G\/112G SerDes clocking<\/figcaption><\/figure>\n<p>Silicon Labs is the first timing supplier to provide fully integrated clock IC solutions for <span class=\"highlight highlight-blue\"><a href=\"http:\/\/www.silabs.com\/56G\" target=\"_blank\" rel=\"noopener\">56G designs<\/a><\/span> that integrate SerDes, CPU and system clocks into a single device. In 56G applications, hardware developers often seek complete clock tree solutions guaranteeing sub-100fs RMS phase jitter to ensure sufficient margin and de-risk product development.<\/p>\n<span class=\"highlight highlight-blue\"><a href=\"https:\/\/engineernewsnetwork.com\/blog\/embedded-world-2018-silicon-labs-unveils-advances-in-wi-fi-bluetooth-mesh-multiprotocol-technology-and-cloud-connectivity\/\" target=\"_blank\" rel=\"noopener\">Silicon Labs<\/a><\/span>\u2019 new clock and oscillator products meet these stringent 56G SerDes requirements today, as well as the needs of emerging 112G serial SerDes designs that will ramp in data center and communications applications in the future.<\/p>\n<p>\u201cSilicon Labs\u2019 new clock generators, jitter attenuators and VCXO\/XOs comprise the industry\u2019s broadest portfolio of frequency-flexible, ultra-low-jitter timing devices for the latest 56G SerDes-based\u00a0 100\/200\/400\/600G communications and data center designs,\u201d said James Wilson, Senior Marketing Director for Silicon Labs\u2019 timing products. \u201cWhether our customers are designing synchronous or free-running systems, we offer the right ultra-high-performance timing solutions to meet their 56G SerDes application needs.\u201d<\/p>\n<p>Silicon Labs\u2019 Si5391 is the industry\u2019s lowest jitter, any-frequency clock generator. It is the only clock generator on the market that can provide all clock frequencies needed in 200\/400\/600G designs from a single IC while delivering sub-100 fs RMS phase jitter performance for 56G SerDes reference clocks.<\/p>\n<p>Featuring up to 12 differential outputs, the Si5391 clock is available in frequency flexible A\/B\/C\/D grade options.<\/p>\n<p>A Precision Calibration P-grade option optimises RMS phase jitter performance with a 69fs (typical) specification for the primary frequencies needed in 56G SerDes designs.<\/p>\n<p>The Si5391 is a true sub-100fs \u2018clock tree on a chip\u2019 solution designed to synthesise all output frequencies from the same IC while meeting 56G PAM-4 reference clock jitter requirements with margin.<\/p>\n<p>Silicon Labs\u2019 Si539x jitter attenuators lead the industry in jitter performance and frequency flexibility.<\/p>\n<p>Designed to meet the exacting specifications and high-performance requirements of Internet infrastructure, these ultra-low jitter clocks reduce cost and complexity for a wide range of timing applications.<\/p>\n<p>Si539x any-frequency jitter attenuating clocks generate any combination of output frequencies from any input frequency while delivering industry-leading jitter performance (90fs RMS phase jitter). Si5395\/4\/2 P-grade devices offer best-in-class jitter (69fs RMS typical phase jitter) for 56G\/112G SerDes clocking applications.<\/p>\n<p>The new Si56x Ultra Series VCXO and XO family is ideal for next-generation high-performance timing applications requiring ultra-low jitter oscillators.<\/p>\n<p>Si56x VCXO\/XOs are customisable to any frequency up to 3GHz, supporting twice the operating frequency range of previous Silicon Labs VCXO products with half the jitter.<\/p>\n<p>The Si56x oscillators are available with single, dual, quad, and I2C-programmable options in industry-standard 5mm x 7mm and 3.2mm x 5mm packages, enabling drop-in compatibility with traditional XO, VCXOs and VCSOs. This family features devices with typical phase jitter as low as 90fs.<\/p>\n<p>Silicon Labs also offers the Si54x Ultra Series XO family for applications requiring tighter stability and guaranteed long-term reliability, such as optical transport networking (OTN), broadband equipment, data centres and industrial systems.<\/p>\n<p>The Si54x XOs are purpose-built for 56G designs, which rely on four-level pulse-amplitude modulation (PAM-4) signalling for serial data transmission to increase the bit rate per channel while keeping the bandwidth constant.<\/p>\n<p>Using an Si54x XO as a low-jitter reference clock maximises signal-to-noise ratio (SNR) headroom, minimises bit errors and enhances signal integrity. The Si54x family offers best-in-class performance, with typical phase jitter as low as 80fs.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Silicon Labs has expanded its timing portfolio to meet the high-performance clocking requirements of 56G PAM-4 SerDes and emerging 112G serial applications. With this portfolio expansion, Silicon Labs is the only timing supplier to offer a comprehensive selection of clock generators, jitter attenuating clocks, voltage-controlled crystal oscillators (VCXOs) and XOs for 100\/200\/400\/600G designs that satisfy &hellip;<\/p>\n","protected":false},"author":1,"featured_media":8236,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[104],"tags":[4631,1322],"class_list":["post-8234","post","type-post","status-publish","format-standard","has-post-thumbnail","","category-electronics","tag-56g-112g-serdes-clocking","tag-silicon-laboratories"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Clocks boost frequency flexibility and jitter performance - Engineer News Network<\/title>\n<meta name=\"description\" content=\"Silicon Labs has expanded its timing portfolio to meet the high-performance clocking requirements of 56G PAM-4 SerDes and emerging 112G serial applications\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.engineernewsnetwork.com\/blog\/jitter-performance\/\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Clocks boost frequency flexibility and jitter performance - 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