SEGGER support for SiFive Insight debug/trace platform

SEGGER continues to strengthen its position in relation to the RISC-V instruction set architecture. 

The company’s products are already fully compatible with SiFive’s RISC-V processor cores, and now its J-Link probes deliver support for the new SiFive Insight debug/trace solution. This includes SiFive’s latest Nexus-based trace implementation, which enables ongoing monitoring and recording of processor instruction execution.

Via SEGGER’s J-Link PLUS, PRO and ULTRA debug probe options, plus the accompanying Ozone debugger and performance analysis software package, engineers are now able to take full advantage of SiFive Insight using on-chip trace functionality. 

Among the relevant features incorporated within the SEGGER debug probes is a backtracing capability (where the full execution history can be easily accessed and stepped through backwards).

More advanced features, like code coverage and profiling, can also be employed – based on the execution counters processed by the J-Link software. 

The Ozone debug software package can subsequently generate detailed code coverage reports for software validation purposes.

“The continued support from SEGGER is a great asset to the RISC-V ecosystem, and the swift adoption of SiFive Insight is of great benefit to chip designers,” says Drew Barbier, Director of Product Marketing at SiFive. “SEGGER has supported SiFive Core IP since 2017 and continues to be a valued partner in the expansion and adoption of RISC-V for embedded solutions. We look forward to continued cooperation as the RISC-V ecosystem continues to grow and evolve.”

“SiFive continues to innovate with solid offerings for the global RISC-V community,” adds Rolf Segger, founder of SEGGER. “We are proud to support its team’s efforts by offering high quality development tools and ensuring that the exciting new features they are introducing can be fully leveraged using our industry-leading Ozone debugger software and J-Link debug probe products.”