Margin tester breaks conventions of PCIe testing

Tektronix, Inc announces a new product category that changes PCI Express testing, transforming time-to-market, cost, and accessibility. 

The new TMT4 Margin Tester’s plug-and-play set-up and easy-to-use interface combine to deliver in minutes results that, up until now, required hours or even days of set-up and testing, often stretching costs to seven figures.

PCIe validation testing

While PCIe testing normally requires complex test systems and engineers with deep expertise and knowledge, the TMT4 Margin Tester enables engineers at all levels of experience to evaluate the health of transmitter (Tx) and receiver (Rx) links faster than ever, greatly reducing time to market and cost of ownership. The platform supports the majority of common PCIe form factors, including CEM, M.2, U.2, and U.3, with testing capabilities of up to 16 lanes across PCIe presets 0-9, using a single standard connector. 

The TMT4 tester is intended to complement full validation and compliance testing systems consisting of oscilloscopes and BERTs, by making it possible to uncover issues earlier in the design process prior to an in-depth examination using traditional equipment.

New technologies are more complex than ever, requiring significant time and expertise to validate them. The new TMT4 Margin Tester enables engineers at all levels of expertise to test PCIe devices across up to 160 combinations of lanes and presets in as little as 20 minutes at Gen 4 speeds. Multi-lane testing capabilities enable users to significantly improve overall testing times by reducing the number of connection changes needed to perform testing.

Features include:  

* Quick Scan mode enables evaluation of link health for Gen 3 or Gen 4 devices, up to 16 lanes, in minutes, not hours or days

 * Custom Scan mode provides deeper insights by enabling users to scan Gen 3 or 4 devices, up to 16 lanes, across PCIe presets 0-9 (up to 160 combinations) in as little as 20 minutes

 * Simple set-up and configuration minimise the need for senior-level engineers to perform link health evaluations of their designs

 * Full Tx/Rx protocol capability that enables link health evaluation of PCIe Gen 3 and Gen 4 communication technologies on both sides of the link in a single box 

 * Multi-lane testing capabilities enable users to significantly improve overall testing times by reducing the number of connection changes needed to perform testing

 * Visibility of link training parameters provides additional insights into which equalisation was used to form the link.

 * Variety of adapters supporting the most common PCIe form factors for easy connection to motherboard and add-in card DUTs including CEM, M.2, U.2 and U.3.