Test chip fabricated in TSMC 7nm process achieves 4400MT/sec data rate 2nd May 2018 Electronics Comments Off on Test chip fabricated in TSMC 7nm process achieves 4400MT/sec data rate 2,189 Cadence Design Systems has prototyped its first IP interface in silicon for a preliminary version of the DDR5 standard being … Read More » Share Facebook Twitter Stumbleupon LinkedIn Pinterest