Microchip, via its Microsemi subsidiary, announces its Smart Embedded Vision initiative that provides solutions for designing intelligent machine vision systems with Microchip’s low-power PolarFire Field Programmable Gate Arrays (FPGAs).
With the announcement, Microchip extends its high-resolution smart embedded vision FPGA offerings with new enhanced high-speed imaging interfaces, an intellectual property (IP) bundle for image processing and an expanded partner ecosystem.
As compute-intensive, vision-based systems are increasingly integrated at the network edge, FPGAs are quickly becoming a preferred flexible platform for next-generation designs.
In addition to requiring high bandwidth processing capabilities, these intelligent systems are deployed in small form factors with tight thermal and power constraints.
The Smart Embedded Vision initiative provides a suite of FPGA offerings that includes IP, hardware and tools for low-power, small form factor machine vision designs across the industrial, medical, broadcast, automotive, aerospace and defence markets.
With the launch of the initiative, Microchip has added the following to further address design requirements for intelligent vision systems:
Serial Digital Interface (SDI) IP – Used to transport uncompressed video data streams over coaxial cabling, this interface comes in multiple speeds: HD-SDI (1.485 Gbps, 720p, 1080i), 3G-SDI (2.970 Gbps, 1080p60), 6G-SDI (5.94 Gbps, 2Kp30) and 12G-SDI (11.88 Gbps, 2Kp60).
1.5 Gbps per lane MIPI-CSI-2 IP – Typically used in industrial cameras, MIPI-CSI-2 is a sensor interface that links image sensors to FPGAs. The PolarFire family supports receive speeds up to 1.5 Gbps per lane and transmit speeds up to 1 Gbps per lane.
2.3 Gbps per lane SLVS-EC Rx – SLVS-EC Rx is an image sensor interface IP supporting high-resolution cameras. Customers can implement a two-lane or eight-lane SLVS-EC Rx FPGA core.
Multi-rate Gigabit MAC – The PolarFire family can support 1, 2.5, 5 and 10 Gbps speeds over an Ethernet PHY, enabling the initiative to meet the need for Universal Serial 10 GE Media Independent Interface (USXGMII) MAC IP with auto-negotiation
6.25 Gbps CoaXPress v1.1 Host and Device IP – CoaXPress is a standard used in high- performance machine vision, medical and in industrial inspection. Aligned with the industry’s roadmap for the standard, Microchip will support CoaXPress v2.0, which doubles the bandwidth to 12.5 Gbps
HDMI 2.0b – The HDMI IP core today supports resolutions up to 4K at 60 fps transmit and 1080p at 60 fps receive.
PolarFire FPGA Imaging IP bundle – Features the MIPI-CSI-2 and includes image processing IPs for edge detection, alpha blending and image enhancement for colour, brightness and contrast adjustments.
Expanded Partner Ecosystem – The Smart Embedded Vision initiative introduces Kaya Instruments, which provides PolarFire FPGA IP Cores for CoaXPress v2.0 and 10 GigE vision, to Microchip’s partner ecosystem. The ecosystem also includes Alma Technology, Bitec and artificial intelligence partner ASIC Design Services, which provides a Core Deep Learning (CDL) framework that enables a power-efficient Convolutional Neural Network (CNN)-based imaging and video platform for embedded and edge computing applications.
PolarFire FPGAs offer 30 to 50 percent lower total power over competing Static Random-Access Memory (SRAM)-based mid-range FPGAs.
With family members ranging from 100K to 500K Logic Elements (LEs), they provide five to 10 times lower static power, making them ideal for a new range of compute-intensive edge devices, including those deployed in thermally- and power-constrained environments.
In addition to new high-speed imaging IP cores and the PolarFire Imaging IP bundle, a new MIPI-CSI2-based machine learning camera reference design is available for smart embedded system implementations.
Based on the PolarFire FPGA imaging and video kit that uses inference algorithms from Microchip partner ASIC Design Services, the reference design is free for customers to evaluate.
All Smart Embedded Vision solutions are supported by the Libero SoC Design Suite, Microchip’s comprehensive development tool.